Multi-step planarizing and polishing method

Abstract

A multi-step planarizing and polishing method includes performing a first and a second polishing steps, wherein one of the two polishing steps is performed using a silica abrasive based slurry, while the other one of the two polishing steps is performed using a CeO2 abrasive based slurry. A third polishing step is further performed using a fixed abrasive pad. Further, the thickness deviation of wafers entering the third polishing step is controlled.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of Invention[0002]The present invention relates to a method for fabricating a semiconductor device. More particularly, the present invention relates to a method for planarizing and polishing a semiconductor wafer.[0003]2. Description of Related Art[0004]In the fabrication of advanced integrated circuits (ICs), it is often necessary to polish a surface of a layer or a structure, such as a semiconductor wafer, to remove topographic irregularities and surface defects including scratches or embedded debris and particles. For example, a dielectric layer may form over a previously patterned layer. The dielectric layer may be used to form an interlevel dielectric or shallow trench isolation. The surface fluctuations and the excessive amount of the deposited dielectric layer may be removed by a planarization process known as chemical mechanical polishing (CMP). It is well aware in the art that providing planar surfaces facilitates the formation of t...

AI Technical Summary

Benefits of technology

[0013]The present invention also provides a multi-step planarizing and polishing method, wherein local planarity and within-die uniformity are improved.

[0025]According to the multi-step planarizing and polishing method of the present invention, improved throughput, good local planarizity and global uniformity can be achieved.

Problems solved by technology

And as the level of integration increases and the feature sizes of semiconductor devices continuously reduce, providing planar surfaces become increasingly important since a non-planar topography may result with photo-printing difficulties and problems in etching and step coverage of openings.

However, many problems are associated with the CMP technique.

The over polishing, however, may result in “dishing” of the trench oxide and “erosion” of the adjacent silicon nitride.

Another problem that may be encountered in the CMP process is the “loading effect” in which an irregular surface is formed on the polished structure due to a deformed polishing pad.

Therefore, the cost is increased and the cycle time is prolonged.

Moreover, reverse masking still suffers from poor uniformity problems.

However, there are also issues associated with this approach, such as drop of the removal rate.

Ultimately, the drop of the removal rate leads to a low throughput.

Moreover, since a polishing process using FA pads operates in a time mode basis, overpolishing due to a thickness variation of the incoming wafers is often resulted.

However, HSS also suffers from removal rate drop and removal rate deviation, which ultimately impacts on the throughput.

However, even combining a “regular” polishing step using silica abrasives with a polishing step using a FA pad, it has been observed that the within-die uniformity remains undesirable.

Further, the thickness deviation of the incoming wafers entering the FA polishing step is high; therefore, overpolishing as commonly occurred in polishing with a FA pad is still resulted.

Since polishing with HSS typically results with high removal rate deviation, the wafer-to-wafer uniformity is undesirable.

Moreover, the thickness deviation of the incoming wafers entering the FA based polishing step is high, the problem of overpolishing remains a great concern.

Further, both the HSS based and the FA based polishing processes exhibit removal rate drop; low throughput is ultimately resulted.

However, completing a polishing process with a HSS based polishing step remains undesirable since the HSS based polishing process exhibits high removal rate deviation and removal rate drop.

Further, global uniformity can not be attained.

In summary, the conventional one step or two-step polishing methods are unable to concurrently achieve global uniformity, local planarity and high throughput.

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