Application Specific Instruction Set Processor for Digital Radio Processor Receiving Chain Signal Processing

Active Publication Date: 2009-03-05
TEXAS INSTR INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Benefits of technology

[0009]This invention is an application specific instruction set processor (ASIP) targeting the high rate FDRX supporting both 16-bit GGE and 8-bit/16 bit WCDMA applications. This ASIP architecture is a modification of a simple RISC with 16-bit instruction width and 32-bit data width by adding multiple custom functional units (ADU) into its data path. The tight coupling between each ADU and the processor core's fetch and decode logic makes it possible to implement each FDRX-specific operation, which would requi

Problems solved by technology

Both GGE and WCDMA applications them meet the challenging data rate requir

Method used

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  • Application Specific Instruction Set Processor for Digital Radio Processor Receiving Chain Signal Processing
  • Application Specific Instruction Set Processor for Digital Radio Processor Receiving Chain Signal Processing
  • Application Specific Instruction Set Processor for Digital Radio Processor Receiving Chain Signal Processing

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Embodiment Construction

[0044]FIG. 2 illustrates the full FDRX for 8-bit WCDMA. FIG. 3 illustrates the full FDRX for 16-bit GGE. Both FIG. 2 and FIG. 3 include the additional two functional blocks: IQMC_AE (IQ Mismatch Adaptive Engine) 201 and 301; and ROC (Residual Offset Cancellation) 202 and 302. Since the data paths are highly reconfigurable, FIGS. 2 and 3 show one worst case in WCDMA and GGE where all blocks are present. The formula on each block shows the corresponding transfer function in the z-domain for is a digital filter (FIR or IIR). For IQMC_CE 105 and IQMC_AE 201 and 301, the algorithms are expressed in the time domain with complex computations.

[0045]Assume the input to the FDRX is a vector {xi, xq} and each component is represented by 8-bit signed integer. The output on each of the ten blocks is labeled on FIG. 2. The computation on each block is presented in the time domain in the following:

[0046](1) RES 101 performs the 8-tap decimation real FIR for both I and Q channels:

y1i[n]=∑i=07cixi[7...

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Abstract

This invention is an application specific integrated processor to implement the complete fixed-rate DRX signal processing paths (FDRX) for a reconfigurable processor-based multi-mode 3G wireless application. This architecture is based on the baseline 16-bit RISC architecture with addition functional blocks (ADU) tightly coupled with the based processor's data path. Each ADU accelerates a computation-intensive tasks in FDRX signal path, such as multi-tap FIRs, IIRs, complex domain and vectored data processing. The ADUs are controlled through custom instructions based on the load/store architecture. The whole FDRX data path can be easily implemented by the software employing these custom instructions.

Description

CLAIM OF PRIORITY[0001]This application claims priority under 35 U.S.C. 119(e)(1) to U.S. Provisional Application No. 60 / 956,616 filed Aug. 17, 2007.TECHNICAL FIELD OF THE INVENTION[0002]The technical field of this invention is data processing in wireless receivers.BACKGROUND OF THE INVENTION[0003]The continuous scaling of transistor size makes it possible to integrate more and more signal processing functionalities into the same silicon with less area overhead. Employing extensive digital signal processing technologies, a digital radio processor (DRP) can process RF signals in the digital domain as much as possible to provide better performance with reduced cost. Based on an all digital PLL (ADPLL) architecture, a digital radio processor integrates all necessary blocks including RF, analog / mixed-signal and digital ones to provide a single-chip solution for GSM / GPRS / EDGE (GGE) and WCDMA applications.[0004]The DRP receiver chain provides the signal processing for the received RF sign...

Claims

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Application Information

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IPC IPC(8): G06F9/30
CPCG06F9/3885G06F9/30036
Inventor XI, JINWENSTASZEWSKI, ROMANTRAN, THANG MINH
Owner TEXAS INSTR INC
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