Application Specific Instruction Set Processor for Digital Radio Processor Receiving Chain Signal Processing

Abstract

This invention is an application specific integrated processor to implement the complete fixed-rate DRX signal processing paths (FDRX) for a reconfigurable processor-based multi-mode 3G wireless application. This architecture is based on the baseline 16-bit RISC architecture with addition functional blocks (ADU) tightly coupled with the based processor's data path. Each ADU accelerates a computation-intensive tasks in FDRX signal path, such as multi-tap FIRs, IIRs, complex domain and vectored data processing. The ADUs are controlled through custom instructions based on the load / store architecture. The whole FDRX data path can be easily implemented by the software employing these custom instructions.

Description

CLAIM OF PRIORITY[0001]This application claims priority under 35 U.S.C. 119(e)(1) to U.S. Provisional Application No. 60 / 956,616 filed Aug. 17, 2007.TECHNICAL FIELD OF THE INVENTION[0002]The technical field of this invention is data processing in wireless receivers.BACKGROUND OF THE INVENTION[0003]The continuous scaling of transistor size makes it possible to integrate more and more signal processing functionalities into the same silicon with less area overhead. Employing extensive digital signal processing technologies, a digital radio processor (DRP) can process RF signals in the digital domain as much as possible to provide better performance with reduced cost. Based on an all digital PLL (ADPLL) architecture, a digital radio processor integrates all necessary blocks including RF, analog / mixed-signal and digital ones to provide a single-chip solution for GSM / GPRS / EDGE (GGE) and WCDMA applications.[0004]The DRP receiver chain provides the signal processing for the received RF sign...

AI Technical Summary

Benefits of technology

[0009]This invention is an application specific instruction set processor (ASIP) targeting the high rate FDRX supporting both 16-bit GGE and 8-bit / 16 bit WCDMA applications. This ASIP architecture is a modification of a simple RISC with 16-bit instruction width and 32-bit data width by adding multiple custom functional units (ADU) into its data path. The tight coupling between each ADU and the processor core's fetch and decode logic makes it possible to implement each FDRX-specific operation, which would require multiple cycles in the general purpose processor's ALU. Designers can implement the FDRX with arbitrary configurations among different blocks shown in FIG. 1 using these custom instructions. The support of 8-bit / 16-bit GGE / WCDMA FDRX is provided by the custom 8-bit multiplier array, which can be configured to perform 4 8-bit multiplications or 1 16-bit multiplication via custom instructions. The ADU also provides single-cycle 8-bit / 16-bit vector processing on the I / Q samples in both real and complex domains.

[0017](6) FILT unit: a multi-cycle FIR processing capability for both 8-bit and 16-bit I / Q sample vectors for GGE / WCDMA which supports multiple FIR types including symmetrical / asymmetrical and real / complex by two vector computation units (VCU) containing multiple 8-bit multipliers with a 5-stage pipelined and dedicated multi-port register file and local sequencer to accelerate the multi-tap FIRs;

[0020]Each ADU is highly customized for accelerating computation intensive tasks in FDRX signal path. These tasks include multi-tap FIRs, IIRs, complex domain and vectored data processing. Custom instructions based on load-store architecture are defined to manipulate these ADUs and the whole FDRX data path can be easily implemented by the software employing these custom instructions.

Problems solved by technology

Both GGE and WCDMA applications them meet the challenging data rate requirements, which cannot be met even using 8-issue high-performance 32-bit DSP.

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