Threshold adjustment for MOS devices by adapting a spacer width prior to implantation

Abstract

Different threshold voltages of transistors of the same conductivity type in a complex integrated circuit may be adjusted on the basis of different Miller capacitances, which may be accomplished by appropriately adapting a spacer width and / or performing a tilted extension implantation. Thus, efficient process strategies may be available to controllably adjust the Miller capacitance, thereby providing enhanced transistor performance of low threshold transistors while not unduly contributing to process complexity compared to conventional approaches in which threshold voltage values may be adjusted on the basis of complex halo and well doping regimes.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to the fabrication of highly sophisticated integrated circuits including transistor structures of different threshold voltages.[0003]2. Description of the Related Art[0004]The manufacturing process for integrated circuits continues to improve in several ways, driven by the ongoing efforts to scale down the feature sizes of the individual circuit elements. A key issue in developing integrated circuits of increased packing density and enhanced performance is the scaling of transistor elements, such as MOS transistor elements, to increase the number of transistor elements in order to enhance performance of modern CPUs and the like with respect to operating speed and functionality. One important aspect in manufacturing field effect transistors having reduced dimensions is the reduction of the length of the gate electr...

AI Technical Summary

Benefits of technology

[0009]Generally, the present disclosure relates to methods and semiconductor devices in which an increase of the Miller capacitance may be selectively obtained for transistor elements requiring a reduced threshold voltage by incorporating, in some illustrative aspects disclosed herein, techniques in the overall process flow in order to adapt a width of sidewall spacers prior to introducing a dopant species for forming drain and source extension regions. In this manner, the overlap and thus the Miller capacitance may be increased, substantially without requiring additional threshold implantation techniques during the definition of the well and halo regions. In other illustrative aspects disclosed herein, in addition to or alternatively to appropriately adapting the spacer width for transistors of the same conductivity type, the tilt angles may be selectively varied for defining the lateral dopant profile of transistors of different threshold voltage, thereby also providing an appropriately adapted Miller capacitance. For example, for low threshold transistors, an additional tilted extension implantation may be performed, thereby not only increasing the lateral penetration depth under the gate electrode structure but also increasing the overall dopant concentration, which may result in a more efficient modification of the Miller capacitance during subsequent anneal techniques. Consequently, an efficient adjustment of threshold voltages of transistors of the same conductivity type may be accomplished by adapting the Miller capacitance on the basis of an appropriate masking regime, which may not unduly contribute to overall process complexity, since, in some illustrative aspects, other masking steps, for instance for appropriately defining different threshold voltage levels by means of halo and well implantations, may be omitted.

Problems solved by technology

A key issue in developing integrated circuits of increased packing density and enhanced performance is the scaling of transistor elements, such as MOS transistor elements, to increase the number of transistor elements in order to enhance performance of modern CPUs and the like with respect to operating speed and functionality.

Although the reduction of the gate length is necessary for obtaining smaller and faster transistor elements, it turns out, however, that a plurality of issues are additionally involved to maintain proper transistor performance for a reduced gate length.

For example, so-called short channel effects may occur for highly scaled transistor elements, resulting in a reduced controllability of the channel region, which may result in increased leakage currents and generally in degraded transistor performance.

One challenging task in this respect, therefore, is the provision of appropriately designed junction regions in the form of shallow junctions, at least at the area in the vicinity of the channel region, i.e., source and drain extension regions, which nevertheless exhibit a moderately high conductivity so as to maintain the resistivity in conducting charge carriers from the channel to a respective contact area of the drain and source regions at a relatively low level while also controlling the parasitic drain / source capacitance and the electric field of the cut-off region.

The introduction of a high dose of dopants into a crystalline substrate area, however, generates heavy damage in the crystal structure, and therefore one or more anneal cycles are typically required for activating the dopants, i.e., for placing the dopants at crystal sites, and to cure the heavy crystal damage.

However, the electrically effective dopant concentration is limited by the ability of the anneal cycles to electrically activate the dopants.

This ability in turn is limited by the solid solubility of the dopants in the silicon crystal and the temperature and duration of the anneal process that are compatible with the process requirements.

Moreover, besides the dopant activation and the curing of crystal damage, dopant diffusion may also occur during the annealing, which may lead to a “blurring” of the dopant profile.

Consequently, for performance-driven transistor elements, the corresponding threshold voltage may also have to be reduced in order to obtain a desired high saturation current at a reduced gate voltage, since the reduced supply voltage may also restrict available voltage swing for controlling the channel of the transistor.

However, the reduction of the threshold voltage, which may typically be accomplished by appropriately doping the well region of the transistor in combination with sophisticated halo implantation processes, which are designed to provide the appropriate dopant gradient at the PN junctions and the overall conductivity of the channel region, may also affect the static leakage currents of the transistors.

That is, by lowering the threshold voltage, typically, the off current of the transistors may increase, thereby contributing to the overall power consumption of an integrated circuit, which may comprise millions of corresponding transistor elements.

In addition to increased leakage currents caused by extremely thin gate dielectric materials, the static power consumption may result in unacceptable high power consumption, which may not be compatible with the heat dissipation capabilities of integrated circuits designed for general purposes.

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