Threshold adjustment for MOS devices by adapting a spacer width prior to implantation

Abstract

Different threshold voltages of transistors of the same conductivity type in a complex integrated circuit may be adjusted on the basis of different Miller capacitances, which may be accomplished by appropriately adapting a spacer width and / or performing a tilted extension implantation. Thus, efficient process strategies may be available to controllably adjust the Miller capacitance, thereby providing enhanced transistor performance of low threshold transistors while not unduly contributing to process complexity compared to conventional approaches in which threshold voltage values may be adjusted on the basis of complex halo and well doping regimes.

Description

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to the fabrication of highly sophisticated integrated circuits including transistor structures of different threshold voltages.

[0003] 2. Description of the Related Art

[0004] The manufacturing process for integrated circuits continues to improve in several ways, driven by the ongoing efforts to scale down the feature sizes of the individual circuit elements. A key issue in developing integrated circuits of increased packing density and enhanced performance is the scaling of transistor elements, such as MOS transistor elements, to increase the number of transistor elements in order to enhance performance of modern CPUs and the like with respect to operating speed and functionality. One important aspect in manufacturing field effect transistors having reduced dimensions is the reduction of the length of the gate electr...

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