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Semiconductor device

a technology of semiconductors and semiconductors, applied in the direction of solid-state devices, digital storage, instruments, etc., can solve the problems of increasing the cost per storage capacity, difficult to substantially reduce power consumption, short data holding time, etc., to achieve the effect of reducing power consumption, storing data for an extremely long time, and avoiding the frequency of refresh operation

Inactive Publication Date: 2013-11-07
YAMAZAKI SHUNPEI +2
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0028]Since the off-state current of a transistor including an oxide semiconductor is extremely low, stored data can be stored for an extremely long time by using the transistor. In other words, power consumption can be adequately reduced because refresh operation becomes unnecessary or the frequency of refresh operation can be extremely low. Moreover, stored data can be stored for a long time even when power is not supplied.
[0029]Further, a high voltage being not necessary to write data, deterioration of the element does not become a problem. Furthermore, data is written depending on the on state and the off state of the transistor, whereby high-speed operation can be easily realized. In addition, there is no need of operation for erasing data.
[0030]Since a transistor including a material which is not an oxide semiconductor can operate at high speed when compared to a transistor using an oxide semiconductor, stored data can be read out at high speed by using the transistor including a material which is not an oxide semiconductor.

Problems solved by technology

Moreover, a transistor included in a storage element has a leakage current and electric charge flows into or out of the capacitor even when the transistor is not selected, so that the data holding time is short.
For that reason, another writing operation (refresh operation) is necessary at predetermined intervals, and it is difficult to substantially reduce power consumption.
Furthermore, since stored data is lost when power supply stops, an additional storage device using a magnetic material or an optical material is needed in order to hold the data for a long time.
However, cost per storage capacity is increased because a circuit such as a flip-flop is used.
Moreover, as in a DRAM, stored data in an SRAM is lost when power supply stops.
However, a gate insulating layer included in a storage element deteriorates by tunneling current generated in writing, so that the storage element stops its function after a predetermined number of writing operations.
However, a complicated peripheral circuit is needed to apply this method.
Moreover, employing such a method does not solve the fundamental problem of lifetime.
In other words, a flash memory is not suitable for applications in which data is frequently rewritten.
Further, it takes a relatively long time to inject or remove electric charge, and it is not easy to increase writing and erasing speed.

Method used

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Examples

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embodiment 1

[0061]In this embodiment, a structure and a manufacturing method of a semiconductor device according to one embodiment of the invention disclosed herein will be described with reference to FIG. 1, FIGS. 2A and 2B, FIGS. 3A to 3H, FIGS. 4A to 4G, FIGS. 5A to 5D, FIG. 6, FIGS. 7A and 7B, FIGS. 8A and 8B, and FIGS. 9A and 9B.

[0062]

[0063]FIG. 1 illustrates an example of a circuit configuration of a semiconductor device. The semiconductor device includes a transistor 160 formed using a material which is not an oxide semiconductor, and a transistor 162 formed using an oxide semiconductor.

[0064]Here, a gate electrode of the transistor 160 is electrically connected to one of a source electrode and a drain electrode of the transistor 162. A first wiring SL (a 1st line, also referred to as a source line) is electrically connected to a source electrode of the transistor 160. A second wiring BL (a 2nd line, also referred to as a bit line) is electrically connected to a drain electrode of the tr...

modification example

[0185]FIG. 6, FIGS. 7A and 7B, FIGS. 8A and 8B, and FIGS. 9A and 9B illustrate modification examples of structures of semiconductor devices. The semiconductor devices in each of which the transistor 162 has a structure different from that described above will be described below as modification examples. That is, the structure of the transistor 160 is the same as the above.

[0186]FIG. 6 illustrates an example of a semiconductor device including the transistor 162 in which the gate electrode 136d is placed below the oxide semiconductor layer 140 and the source / drain electrodes 142a and 142b are in contact with a bottom surface of the oxide semiconductor layer 140. Note that the planar structure can be changed as appropriate to correspond to the cross section; therefore, only the cross section is shown here.

[0187]A big difference between the structure in FIG. 6 and the structure in FIG. 2A is the position at which the oxide semiconductor layer 140 is connected to the source / drain electr...

embodiment 2

[0213]In this embodiment, a circuit configuration of a semiconductor device according to one embodiment of the present invention and an operation method thereof will be described.

[0214]FIG. 10 illustrates an example of a circuit diagram of a memory element (hereinafter, also referred to as a memory cell) included in the semiconductor device. A memory cell 200 illustrated in FIG. 10 includes a third wiring 51 (a first signal line), a fourth wiring S2 (a second signal line), a fifth wiring WL (a word line), a transistor 201, a transistor 202, and a transistor 203. The transistor 201 and the transistor 203 are formed using a material which is not an oxide semiconductor and the transistor 202 is formed using an oxide semiconductor. Here, the transistor 201 and the transistor 203 are preferably formed to have a structure similar to that of the transistor 160 in Embodiment 1. In addition, the transistor 202 is preferably formed to have a structure similar to that of the transistor 162 in ...

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Abstract

It is an object to provide a semiconductor having a novel structure. In the semiconductor device, a plurality of memory elements are connected in series and each of the plurality of memory elements includes first to third transistors thus forming a memory circuit. A source or a drain of a first transistor which includes an oxide semiconductor layer is in electrical contact with a gate of one of a second and a third transistor. The extremely low off current of a first transistor containing the oxide semiconductor layer allows storing, for long periods of time, electrical charges in the gate electrode of one of the second and the third transistor, whereby a substantially permanent memory effect can be obtained. The second and the third transistors which do not contain an oxide semiconductor layer allow high-speed operations when using the memory circuit.

Description

TECHNICAL FIELD[0001]The invention disclosed herein relates to a semiconductor device using a semiconductor element and a method for manufacturing the semiconductor device.BACKGROUND ART[0002]Storage devices using semiconductor elements are broadly classified into two categories: volatile memory devices that lose stored data when power supply stops, and non-volatile memory devices that retain stored data even when power is not supplied.[0003]A typical example of a volatile storage device is a DRAM (dynamic random access memory). A DRAM stores data in such a manner that a transistor included in a storage element is selected and electric charge is stored in a capacitor.[0004]When data is read from a DRAM, according to the above-described principle, electric charge in a capacitor is lost; thus, another writing operation is necessary every time data is read. Moreover, a transistor included in a storage element has a leakage current and electric charge flows into or out of the capacitor ...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L27/088
CPCG11C11/404G11C16/02H01L27/0207H01L27/115G11C11/405H01L27/1156H01L27/1225H01L27/088H01L27/1052H01L27/11517H10B99/00H10B41/00H10B41/70H10B69/00H01L27/0688
Inventor YAMAZAKI, SHUNPEIKOYAMA, JUNKATO, KIYOSHI
Owner YAMAZAKI SHUNPEI
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