Methods for reducing thermal resistance of carbon nanotube arrays or sheets
a carbon nanotube and thermal resistance technology, applied in the direction of solid-state devices, basic electric elements, transportation and packaging, etc., can solve the problems of reducing the thermal resistance of carbon nanotube arrays or sheets, limiting the performance of cnt tims, and affecting the electrical performance of the device, so as to reduce the electrical output, improve the electrical and thermal performance, and prevent the effect of heat rejection
Active Publication Date: 2020-08-06
GEORGIA TECH RES CORP
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Benefits of technology
The coated CNT arrays or sheets exhibit reduced thermal resistance, mechanical durability, and increased shear attachment strength, making them suitable for high-power density devices and repeated cycling applications without significant thermal degradation.
Problems solved by technology
As the semiconductor industry continually strives to increase the power density of single chip packages, thermal management remains a critical challenge toward realizing both performance and reliability metrics.
One of the problems inhibiting effective thermal management is the several interfaces that can exist between the chip and heal sink.
However, even in this arrangement CNT TIMs demonstrated limited performance due to the presence of high thermal contact resistances between the CNT tips and opposing surfaces.
While these techniques have in some cases produced CNT TIMs with thermal resistances approaching those of conventional TIMs, they often require high-cost materials, such as Au or in, and processing, including metal thin film deposition, high temperature and high pressure bonding, and even exposure to microwave radiation, that aren't favorable for large-scale implementation.
Moreover, these processes typically result in a permanent modification to the CNT tips which cannot be reworked or removed.
Method used
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Preparation and Coating of Carbon Nanotube Arrays
[0113]Preparation of Carbon Nanotube Arrays
[0114]Vertical forests of carbon nanotubes (CNTs) were grown on single crystal Si substrates cut into 1×1 cm squares. Ti, Al, Fc films in thicknesses of 30, 10, 3 nm, respectively, were evaporated onto the Si as support and catalyst layers for CNT growth. Afterwards the CNTs were grown using a low-pressure chemical vapor deposition process at 850° C. and 10 mbar in an Aixtron Black Magic® reactor with C2H2 as the carbon source gas. The growth time was varied from 3-15 min to grow forests of multiwall CNTs ranging from 5-150 μm in height with an average CNT diameter of 8 nm.
[0115]CNT forests were also grown on both sides of 10 μm thick Al foil (Alfa Aesar 41798) to create a thermal interposer. An identical growth process was employed except 100 nm of Ni was added to the bottom of the catalyst stack as a diffusion barrier and the temperature of the growth stage was lowered to 750° C. (a pyromet...
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Abstract
Carbon nanotube (CNT) forests or sheets coated and / or bonded at room temperature with one or more coatings were measured to produce thermal resistances that are on par with conventional metallic solders. These results were achieved by reducing the high contact resistance at CNT tips and / or sidewalls, which has encumbered the development of high-performance thermal interface materials based on CNTs. Resistances as low as 4.9±0.3 mm2-K / W were achieved for the entire polymer-coated CNT interface structure.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims priority to U.S. Ser. No. 61 / 537,253 entitled “Methods of Bonding Nanostructures with Nanoscale Polymer Coatings”, riled on Sep. 21, 2011. The content of the above-referenced application is incorporated by reference in its entirety.FIELD OF THE INVENTION[0002]This invention is in the field of carbon nanotube arrays or sheets, particularly coated carbon nanotube arrays or sheets exhibiting reduced thermal resistance and methods of making and using thereof.BACKGROUND OF THE INVENTION[0003]As the semiconductor industry continually strives to increase the power density of single chip packages, thermal management remains a critical challenge toward realizing both performance and reliability metrics. One of the problems inhibiting effective thermal management is the several interfaces that can exist between the chip and heal sink. Specifically, the thermal resistance of the thermal interlace materials (TIMs) that are cur...
Claims
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IPC IPC(8): H01L23/373C25D7/00H01L23/42
CPCH01L23/42H01L2924/0002Y10T428/30B82Y30/00Y10T428/24H01L23/373C25D7/006H01L23/3735H01L2924/00
InventorCOLA, BARATUNDESINGH, VIRENDRABOUGHER, THOMAS L.TAPHOUSE, JOHN H.
OwnerGEORGIA TECH RES CORP