Semiconductor device and method of fabricating same
a semiconductor and semiconductor technology, applied in the direction of solid-state devices, transistors, basic electric elements, etc., can solve the problems of unstable interface state, and disadvantageous long-term stability of electrical characteristics of conventional mosfets, so as to reduce the variation of threshold voltage vth, facilitate fabrication, and high-reliable semiconductor
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first preferred embodiment
[0074]FIG. 1 is a fragmentary plan view of a power IGBT according to a first preferred embodiment of the present invention. FIG. 2 is a fragmentary cross-sectional view taken along the line II—II of FIG. 1. FIG. 3 is a fragmentary plan view taken along the line III—III of FIG. 2 at the surface of a semiconductor body. FIG. 4 is a fragmentary plan view illustrating a plan configuration of a gate electrode shown in FIG. 1. In the fragmentary plan view of the gate electrode in FIG. 4, only the gate electrode and portions formed simultaneously with the gate electrode are illustrated and other portions are not illustrated.
[0075]In FIGS. 1 and 2, the reference numeral 1 designates a P+ substrate serving as a second semiconductor layer; 2 designates an N+ layer; 3 designates an N− layer. The N+ layer 2 and the N− layer 3 form a first semiconductor layer. The reference numeral 4 designates a semiconductor body comprised of the P+ substrate 1, the N+ layer and the N− layer 3; 5 designates a ...
second preferred embodiment
[0131]FIG. 16 is a fragmentary plan view of the IGBT according to a second preferred embodiment of the present invention. FIG. 17 is a fragmentary cross-sectional view taken along the line XVII—XVII of FIG. 16.
[0132]Referring to FIGS. 16 and 17, the IGBT comprises the surface protective film 14 formed in the gate wiring area 32 and the device peripheral area 30.
[0133]The emitter electrode 10 is electrically isolated from the gate interconnection line 9 by a narrow trench. The emitter electrode 10 and the gate interconnection line 9 which are Al—Si sputtering film are easily scratched, for example, when the semiconductor device is handled by a handling device during the fabrication process, resulting in shorting of the emitter electrode 10 and the gate interconnection line 9. However, such a failure is prevented by the surface protective film 14 extending to the surface of the narrow trench. In addition, since there is no channel regions serving as cells under the gate wiring area 32...
third preferred embodiment
[0135]The third preferred embodiment according to the present invention includes an IGBT device structure identical with the conventional structure of FIG. 19 but fabricated by the process corresponding to that of FIG. 5 and FIGS. 6 to 12.
[0136]Specifically, the third preferred embodiment is similar to the first preferred embodiment in the process steps between the formation of the semiconductor body 4 (FIG. 6) and the electrode formation by Al—Si sputtering (FIG. 11). Then radiation is performed for lifetime control, and heat treatment is performed to eliminate distortion, and the surface protective film 14 is finally formed on the device top surface.
[0137]The surface protective film 14 on the device top surface is a semi-insulation silicon nitride film formed by the P-CVD process to cover the IGBT surface except the emitter wire bonding region 13, the gate interconnection line, and the gate bonding pad which is a part of the gate interconnection line.
[0138]As concluded from the C-...
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