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Method for fabricating a semiconductor storage device having an increased dielectric film area

a semiconductor storage device and dielectric film technology, applied in semiconductor devices, capacitors, electrical equipment, etc., can solve the problems of unsatisfactory capacitance increase, unavoidable complexity of fabrication steps, and increase the number of fabrication steps. , to achieve the effect of increasing the capacitance of floating gate electrodes or memory cell capacitors, high reliability, and simple method of fabrication

Inactive Publication Date: 2010-12-21
INTELLECTUAL VENTURES I LLC +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

"The present invention provides a semiconductor device with a composite gate structure memory cell or a stacked memory cell capacitor that increases the capacitance of the floating gate electrode or the memory cell capacitor and has high reliability. The semiconductor device includes an element active region defined by forming an element isolation structure on a semiconductor substrate, an insulating film formed on the semiconductor substrate in the element active region, a conductive film formed on the insulating film and capacitively coupled with the charge storage film. The semiconductor device also includes a method of fabricating the semiconductor device with the composite gate structure memory cell or the stacked memory cell capacitor."

Problems solved by technology

First, in the prior art disclosed in Japanese Patent Laid-Open No. 5-110107, the fine undulations on the floating gate electrode are formed under specific conditions by CVD. Therefore, the fabrication steps are complicated to set the CVD conditions. Additionally, since these undulations are very fine, the effect of increasing the capacitance is not satisfactory.
Therefore, it is unavoidable to complicate the fabrication steps and increase the number of the fabrication steps.
Also, the end point of etching for forming the recess is difficult to determine.
Accordingly, the fabrication steps are complicated and the number of the fabrication steps is increased.
Furthermore, the end point of the etching cannot be easily determined.

Method used

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  • Method for fabricating a semiconductor storage device having an increased dielectric film area
  • Method for fabricating a semiconductor storage device having an increased dielectric film area
  • Method for fabricating a semiconductor storage device having an increased dielectric film area

Examples

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first embodiment

[0050]The arrangement of a memory cell of an EEPROM according to the first embodiment of the present invention and a method of fabricating the same will be described below. FIGS. 1A to 1G and 2A to 2J are side sectional views showing the fabrication steps of the EEPROM memory cell according to the first embodiment. FIG. 3 is a schematic plan view showing a memory cell region of the EEPROM. A section I—I in FIG. 3 corresponds to FIGS. 1A to 1G; and a section II—II, to FIGS. 2A to 2J.

[0051]First, the surface of a p-type silicon semiconductor substrate 1 is selectively oxidized by a so-called LOCOS process to form a field oxide film 2. Consequently, element isolation is achieved on the p-type silicon semiconductor substrate 1 to define element formation regions 3.

[0052]Subsequently, the element formation regions on the p-type silicon semiconductor substrate 1 are thermally oxidized to form a tunnel oxide film 4 having a thickness of about 100 Å, thereby obtaining the state shown in FIG...

second embodiment

[0082]The arrangement of an EEPROM according to the second embodiment of the present invention and a method of fabricating the same will be described below. FIGS. 8A to 8D are side sectional views showing the steps in fabricating a memory cell of the EEPROM according to the second embodiment. FIG. 9 is a schematic plan view showing a memory cell region of this EEPROM. A section I—I in FIG. 9 corresponds to FIGS. 8A to 8D. The same reference numerals as in the EEPROM of the first embodiment denote the same parts, and a detailed description thereof will be omitted.

[0083]This second embodiment differs from the first embodiment in that after a polysilicon film 5 is formed, the surface of the polysilicon film 5 is planarized by chemical mechanical polishing (CMP) before the step of forming a photoresist 6.

[0084]FIG. 8A is a view corresponding to the step shown in FIG. 2B of the first embodiment. Referring to FIG. 8A, the polysilicon film 5 having a thickness of about 1,000 Å is formed by...

third embodiment

[0106]The arrangement of a stacked capacitor cell structure DRAM according to the third embodiment of the present invention and a method of fabricating the same will be described below. FIGS. 10A to 10K are side sectional views showing the steps in fabricating two adjacent DRAM memory cells in the third embodiment. FIG. 11 is a schematic plan view showing these DRAM memory cell regions. A section I—I in FIG. 11 corresponds to FIGS. 10A to 10K.

[0107]First, as shown in FIG. 10A, the surface of a p-type silicon semiconductor substrate 31 is selectively oxidized by a so-called LOCOS process to form a field oxide film 32. Consequently, element isolation is achieved on the p-type silicon semiconductor substrate 31 to define two element formation regions 32.

[0108]Subsequently, the surface of the element formation regions 32 is thermally oxidized to form a gate oxide film 34 having a thickness of about 130 Å. Thereafter, a polysilicon film 35 is formed on the entire surface by CVD.

[0109]The...

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Abstract

A semiconductor device of the present invention is a semiconductor memory having a charge storage film. Recesses or holes which effectively increase the capacitance of a floating gate or a memory cell capacitor are formed in the charge storage film. These recesses or holes are formed at the same time the floating gate electrode or the lower electrode of the capacitor is isolated into the form of islands. A dielectric film and a polysilicon film is formed on the isolated island floating gate electrodes or lower electrodes. These recesses or holes increase the surface area of the dielectric film and improve the write and erase characteristics of a memory cell.

Description

[0001]This application is a divisional of U.S. patent application Ser. No. 09 / 059,590 filed Apr. 4, 1998 now U.S. Pat. No. 6,288,423.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a semiconductor device including a memory cell having a composite gate structure or a semiconductor device including a stacked memory cell capacitor and a method of fabricating the same.[0004]2. Description of the Related Art[0005]Conventionally, several improvements have been made to improve the write and erase characteristics of a memory cell of an EEPROM or the like having a floating gate structure or a memory cell capacitor.[0006]As an example, in prior art disclosed in Japanese Patent Laid-Open No. 5-110107, at least a portion of a polysilicon film as a floating gate electrode is formed by CVD under conditions by which a larger number of fine undulations are formed on the surface of the floating gate electrode, and an insulating interlayer and a contro...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): H01L21/461H01L21/8247H01L21/02H01L21/28H01L21/76H01L29/423H01L29/788H01L29/792H10B12/00H10B20/00H10B69/00
CPCH01L28/92H01L29/42324Y10S438/947H01L29/40114H10B12/033H10B53/30H10B41/30H10B43/30
Inventor SUGAYA, FUMITAKA
Owner INTELLECTUAL VENTURES I LLC