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Solid electrolytic capacitor and method of manufacturing the same

A technology of solid electrolytic capacitors and manufacturing methods, applied in the direction of solid electrolytic capacitors, electrolytic capacitors, capacitors, etc., can solve problems such as low ESL, and achieve excellent high-frequency response characteristics

Inactive Publication Date: 2008-03-26
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, these existing solid electrolytic capacitors have become an obstacle to further lowering the ESL because the electrical connection terminals and lead wires necessary for mounting on the circuit board form resistance and inductance components.

Method used

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  • Solid electrolytic capacitor and method of manufacturing the same
  • Solid electrolytic capacitor and method of manufacturing the same
  • Solid electrolytic capacitor and method of manufacturing the same

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0045] In FIGS. 1 to 4 , a capacitive element 1 includes a porous valve metal sheet 3 other than a plurality of electrode parts 2 , and a dielectric layer provided on the porous surface of the valve metal sheet 3 . 4. The solid electrolyte layer 5 provided on the dielectric layer 4 , the current collector layer 6 provided on the solid electrolyte layer 5 , and the insulating part 7 provided between the electrode part 2 and the current collector layer 6 . Here, the part where the electrode part 2 stands out is called the electrode showing part 25 . The electrode display part 25 and the current collector layer 6 are located on the same surface of the valve metal sheet 3 , and the electrode display part 25 and the current collector layer 6 are electrically insulated by the insulating part 7 .

[0046] In addition, although the capacitive element 1 may have the above-mentioned configuration, it is preferable to form another metal layer as the first connection terminal 8 on the abo...

Embodiment approach 2

[0060]The basic configuration of the second embodiment is the same as that of the first embodiment, except that connection bumps 13 made of gold, solder or tin are provided on the first connection terminal 8 and the second connection terminal 9 for easy connection with semiconductor components. , 14. The connection bumps 13 and 14 are formed by providing an insulating film 16 with an opening 15 in the portion where the connection bumps 13 and 14 are formed in order to keep the pad pitch constant.

[0061] By intersecting connection terminals 8 and 9 on the same plane of the chip-shaped solid electrolytic capacitor in this way, lower ESR and lower ESL can be achieved, resulting in a solid electrolytic capacitor excellent in high-frequency response characteristics.

[0062] The solid electrolytic capacitor shown in FIG. 6 is a sheet-shaped solid electrolytic capacitor, and connection bumps 13 and 14 are provided on both sides.

[0063] In addition, connection bumps 13 and 14 ma...

Embodiment approach 3

[0069] A third embodiment will be described using FIG. 9 . As shown in FIG. 9 , the capacitive element 1 of the present embodiment includes a valve metal sheet 3 formed by forming tantalum powder into a sheet shape and sintering the valve metal sheet 3 . The method of forming the barrier film does not allow the reaction solution to immerse, and the dielectric layer formed by anodic oxidation on the part other than the electrode display part 25, the conductive polymer or the solid electrolyte layer such as manganese dioxide formed on the dielectric layer, and the solid electrolyte layer formed on the solid A current collector layer of carbon and silver paste is formed on the electrolyte layer, an insulating part 7 arranged around the electrode display part 25, a first connection terminal 8 connected to the electrode part 2 arranged in the insulating part 7, and a set The second connection terminal 9 is connected to the current collector layer around the insulating portion 7 . ...

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PUM

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Abstract

A solid electrolytic capacitor, comprising a porous valve metal sheet, a dielectric layer formed on the porous part thereof, a solid electrolytic layer formed on the dielectric layer, a collector layer and an electrode exposed part formed on the solid electrolytic layer, and an insulation part for electrically insulating the electrode exposed part from the collector layer, wherein the electrode exposed part and the collector layer are formed on the same surface of the valve metal sheet, and the capacitor elements thus obtained can be stacked on each other, whereby the solid electrolytic capacitor having a small size, large capacity, and excellent high frequency responsiveness can be provided.

Description

technical field [0001] The invention relates to a solid electrolytic capacitor used in various electronic instruments and a manufacturing method thereof. Background technique [0002] Recently, with the miniaturization and high frequency of electronic equipment, capacitors are also required to be smaller and larger, with low ESR (equivalent series resistance) and low ESL (equivalent series inductance). Conventionally, chip-type capacitors described in US Patent No. 5,377,073 and Japanese Patent Application Laid-Open No. 11-274002 are known as large-capacity multilayer solid electrolytic capacitors. However, in these conventional solid electrolytic capacitors, resistance and inductance components are formed by electrical connection terminals and lead wires necessary for mounting on circuit boards, which hinders the further reduction of ESL. [0003] An object of the present invention is to provide a large-capacity solid electrolytic capacitor mounted on a circuit board, capa...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01G9/052H01G9/04H01G9/07H01G9/025H01G9/08H01G9/012H01G9/00H01G9/15
CPCH01G9/15H01G9/012
Inventor 木村涼三木胜政御堂勇治藤井达雄益见英树
Owner PANASONIC CORP