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Double medium SOI pressure resistant structure with window and its SOI power device

A power device, dual-dielectric technology, applied in the direction of electric solid state devices, semiconductor devices, electrical components, etc., can solve the problems of difficult process, low breakdown voltage and self-heating effect.

Inactive Publication Date: 2009-03-18
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But SOI devices have two important disadvantages: lower breakdown voltage and self-heating effect
However, for the traditional PSOI structure, the withstand voltage above 600V requires a buried oxide layer of more than 4 μm and linear doping in the thin drift region to achieve, and the process is relatively difficult. For related content, please refer to Tadikonda R, Hardikar S, Narayanan EMS. Realizing highbreakdown voltages(>600V)inpartial SOI technology. Solid-State Electronics, 2004, 48: 1655

Method used

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  • Double medium SOI pressure resistant structure with window and its SOI power device
  • Double medium SOI pressure resistant structure with window and its SOI power device
  • Double medium SOI pressure resistant structure with window and its SOI power device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0052] Embodiment 1: SOI structure with double dielectric buried layer

[0053] Figure 5 It is a schematic diagram of the SOI structure with double dielectric buried layers according to the present invention.

[0054] Such as Figure 5 As shown, 1 is the substrate layer, 2 is the first dielectric layer (buried layer), 3 is the active semiconductor layer (S layer), 14 is the second dielectric layer (buried layer), and 15 is the intermediate layer. The intermediate layer 15 is located between the first dielectric layer (buried layer) 2 and the second dielectric layer (buried layer) 14, the other side of the first dielectric layer is connected to the active semiconductor layer 3, and the other side of the second dielectric layer 14 is connected to the The substrate layer 1 is connected. The first dielectric layer has a window which can be filled with intermediate layer material or active layer material.

Embodiment 2

[0055] Embodiment 2: SOI LDMOS device structure with double dielectric buried layer

[0056] Image 6 It is a structural schematic diagram of the SOI LDMOS device with double dielectric buried layers according to the present invention, Figure 7 It is a longitudinal electric field distribution diagram of the SOI LDMOS device with double dielectric buried layers according to the present invention. Figure 8 a is a two-dimensional equipotential diagram of a conventional structure SOI LDMOS device when it breaks down. Figure 8 b is a two-dimensional equipotential diagram at the time of breakdown of the SOI LDMOS device with double dielectric buried layers according to the present invention.

[0057]Such as Image 6 -shown in 8, 1 is the substrate layer, 2 is the first dielectric layer (buried layer), 3 is the active semiconductor layer (S layer), 4 is the dielectric isolation region, 5 is the gate oxide layer, 6 is the gate electrode, 7 For p (or n) well, 8 for n + (or p +...

Embodiment 3

[0058] Embodiment 3: SOI IGBT device structure with double dielectric buried layer

[0059] Figure 9 It is a structural schematic diagram of the SOI IGBT device with double dielectric buried layers according to the present invention.

[0060] Such as Figure 9 As shown, 1 is the substrate layer, 2 is the first dielectric layer, 3 is the active semiconductor layer (S layer), 6 is the gate electrode, 7 is the p (or n) well, and 8 is the n + (or p + ) cathode area, 9 is n + (or p + ) anode region, 14 is the second dielectric layer (buried layer), 15 is the intermediate layer, 17 is the anode, 18 is the cathode, and 19 is the p (or n) well. The intermediate layer 15 is located between the first dielectric layer (buried layer) 2 and the second dielectric layer (buried layer) 14 . The other side of the first dielectric layer is connected to the active semiconductor layer 3 , and the other side of the second dielectric layer 14 is connected to the substrate layer 1 . The firs...

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Abstract

This invention provides a double-dielectric layer SOI pressure structure with a window used in power devices and SOI power devices characterizing that the structure contains two layers of dielectric layers filled with semiconductor or semi-insulation mterials in between and the first layer has a window, when a reverse bias voltage is applied onto the device, the interface charge formed by the up and down interfaces of the middle layer increases the field strength of the second layer, and the exixtance of the window modulates the field of the drift region so as to increase the anti-pressure ability and path of heat conduction, so its self-heating effect depends on the thickness of the second layer, which can become thinner if it is not broken down to release self-heating effect.

Description

technical field [0001] The dual-dielectric SOI voltage-resistant structure with windows and the SOI power device adopting the voltage-resistant layer structure belong to the technical field of semiconductor power devices, and particularly relate to the technical field of SOI (Semiconductor On Insulator) power device voltage-resistant technology. Background technique [0002] SOI (Silicon on Insulator) power devices (SOI power devices for short) have higher operating speed and integration, better insulation performance, stronger radiation resistance and no thyristor self-locking effect, so SOI power devices are used in Applications in the VLSI field have received widespread attention. But SOI devices have two important disadvantages: lower breakdown voltage and self-heating effect. The breakdown voltage of an SOI device depends on the lower of the lateral breakdown voltage and the vertical breakdown voltage. The lateral withstand voltage design of SOI power devices follows ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/12
Inventor 罗小蓉张波李肇基杨寿国詹瞻
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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