Matrix multiplication parallel computing system based on multi-FPGA

A matrix multiplication and parallel computing technology, applied in the field of FPGA technology and parallel computing, can solve the problems of difficult to guarantee system electromagnetic compatibility, deterioration of signal integrity, increase of power consumption, etc., to achieve improved computing performance, low hardware resource requirements, The effect of low communication overhead

Inactive Publication Date: 2007-12-19
ZHEJIANG UNIV
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Problems solved by technology

[0005] Although a single FPGA chip has achieved high computing performance, due to the limitation of semiconductor technology, the speed and performance of the device cannot be infinitely improved.
Moreover, due to the application of high-speed devices, it also brings a series of new problems to the design and reliability of the system, such as increased power consumption, deterioration of signal integrity, and difficulty in ensuring the electromagnetic compatibility of the system, etc.

Method used

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  • Matrix multiplication parallel computing system based on multi-FPGA
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  • Matrix multiplication parallel computing system based on multi-FPGA

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Embodiment Construction

[0029] As shown in Figures 1 and 2, a matrix multiplication parallel computing system based on multi-FPGA and adopting a master-slave distributed structure uses an embedded processor as the main processor 420, and adopts Ethernet or RapidIO interconnection technology. The interconnection topology constitutes a master-slave distributed multi-FPGA matrix multiplication parallel computing system. The interconnection technology of Ethernet and RapidIO supports the multicast transmission mode. When multiple processing units 410 need the same data, the main processor 420 uses the multicast transmission mode through the Ethernet switch or the RapidIO switch 430 to send the data to all these processing units. Compared with other point-to-point interconnect technologies, such as PCI-e, the system has lower communication overhead.

[0030] The main processor 420 includes a data sending module 510 , a command sending module 520 , a response receiving module 530 and a data receiving modu...

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Abstract

A matrix multiplication parallel calculation system based on multi-FPGA is prepared as utilizing FPGA as processing unit to finalize dense matrix multiplication calculation and to raise sparse matrix multiplication calculation function, utilizing Ethernet and star shaped topology structure to form master-slave distributed FPGA calculation system, utilizing Ethernet multicast-sending mode to carry out data multicast-sending to processing unit requiring the same data and utilizing parallel algorithm based on line one-dimensional division output matrix to carry out matrix multiplication parallel calculation for decreasing communication overhead of system.

Description

technical field [0001] The invention relates to FPGA technology and parallel computing technology, in particular to a matrix multiplication parallel computing system based on multiple FPGAs. Background technique [0002] Matrix multiplication operation is a basic operation in scientific computing, widely exists in process control, image processing, digital signal processing and other fields, and is usually the most time-consuming key operation in the calculation process. The time complexity of matrix multiplication calculation is high, usually O(N 3 ), its computing performance directly affects the overall performance of the system. [0003] The previous matrix multiplier is usually implemented by a general-purpose processor or a digital signal processor (DigitalSignal Processor, DSP). General-purpose processors and DSPs have the advantages of relatively mature technology, complete implementation tools, and simple programming. However, due to the limitations of their inter...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/173H04L12/00
Inventor 陈耀武田翔
Owner ZHEJIANG UNIV
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