Channel structure of high voltage NMOS field transistor in EEPROM peripheral circuit and manufacturing method thereof

Abstract

The present invention discloses a trench structure for medium and high voltage NMOS field transistor of EEPROM peripheral circuit, which is filled with boron ions. Production technique of the trench structure lies in that in current technical flows, a trench area is opened through photo-etching. In synchronization with light dope / boron implantation into high-voltage PMOS transistor, boron ions are implanted into the trench. The present invention ensures more effective field isolation, reduces unit area and improves chip integration.

Description

technical field [0001] The invention relates to a channel structure of a high-voltage NMOS (N-type metal oxide semiconductor) field transistor (Field Transistor) in an EEPROM peripheral circuit; the invention also relates to a manufacturing process method of the channel structure. Background technique [0002] With the increasing development of semiconductor manufacturing technology, the competition in integrated circuit design has become increasingly fierce, especially in the design of memory cells, in order to improve competitiveness, it is necessary to reduce the cell area as much as possible and simplify the manufacturing process. In a memory cell, a large area is used for isolation between cells. If the isolation distance between cells can be shortened, the cell area will be effectively reduced. [0003] In EEPROM (Electrically Erasable Programmable Read-Only Memory) cells, the size of the cells turns out to be smaller, so the isolation size is also required to be small...

AI Technical Summary

Problems solved by technology

Since the doping concentration of the N well of the memory cell is not high, in order to reduce the isolation size, a field ion implantation is usually performed under the field oxide layer, which requires an additional photolithography and increases the process cost.

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