Wafer packaging construction with array connecting pad and method of manufacturing the same

Abstract

The present invention relates to a wafer packaging with array pads and its processing method. The wafer packaging mainly includes even numbers of wire-bonded pads, a wafer, even numbers of welding line and a sealing colloid. An upper and a lower combination layers are separately formed on cores of the wire-bonded pads, in which materials of the cores include copper. These welding lines electric connect the wafer with the upper combination layer of the wire-bonded pads. The sealing colloid seals these welding lines, cores and upper combination layers, in which only the lower combination layers are exposed out of the sealing colloid. The present invention can solve the former rusting problem of exposed cutting surface of pins in non-external-pin wafer packaging of conductor frame substrate, and has array pads which can achieve high density of wafer packaging. The processing method of the present invention keeps using a rigid conductive mold in packaging process to carry steps of electroforming, wafer attaching, wire bonding and packaging to achieve coherence of the packaging process.

Description

technical field [0001] The present invention relates to a packaging structure of a semiconductor chip, in particular to a packaging structure that can solve the problem of rusting on the exposed cutting surface of the pins in the conventional chip packaging structure without external pins on the lead frame base, and has an array of pads, which can achieve high density. Chip packaging, and continuous use of a rigid conductive template in the packaging process for electroforming, die bonding, wire bonding, and packaging steps, which can achieve consistent packaging operations. A chip packaging structure with array pads without external pins and its manufacturing method . Background technique [0002] In the prior known packaging technology, a lead frame base wafer package structure is a pinless type. The lower surface of the pin in the lead frame is bonded to the outer surface, replacing the outer pin of the conventional lead frame, and has the advantage of smaller surface fo...

AI Technical Summary

Problems solved by technology

These exposed surfaces 116 cannot be covered and protected by the electroplating layer 115 according to the existing manufacturing process, so it is easy to start rusting from these exposed surfaces 116, which affects the reliability of the product

In addition, the exposed surface 116 of these pins 111 will also cause interference to high-frequency signals, forming an antenna effect

Furthermore, as shown in FIG. 2, since each outer end of these pins 111 must extend to the side of the sealing body 140, the arrangement of these pins can only be single row or multi-row staggered. arrangement, and cannot further achieve high-density chip packaging

[0005] It can be seen that the above-mentioned existing chip packaging structure and its manufacturing method obviously still have inconvenience and defects in product structure, manufacturing method and use, and need to be further improved urgently.

In order to solve the above-mentioned problems, the relevant manufacturers have tried their best to find a solution, but no suitable design has been developed for a long time, and there is no suitable structure and method for general products and methods to solve the above-mentioned problems. This is obviously a problem that relevant industry players are eager to solve

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