Etch stop layer and its forming method

Abstract

The invention relates to a method for forming an etch stop layer, which comprises an etch stop layer formed on a substrate; the etch stop layer is silicon nitride, the stress range of which is from -1, 600 to -2, 000MPa and the stress of which is compressive stress. The invention further provides a structure of a semiconductor device and a manufacturing method thereof. The invention adopts the silicon nitride with a high stress as the etch stop layer. As the silicon nitride has a relative high compactness, and at the same time, the compressive stress of the silicon nitride with a high stress can neutralize a tensile stress of a dielectric layer with a low specific inductive capacity, interface characteristics between the dielectric layer and the dielectric layer, Cu and the dielectric layer are changed, thus realizing the object of increasing the breakdown voltage between layers of the dielectric layer and the reliability of the device.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to an etching barrier layer and a forming method thereof. Background technique [0002] With the development of IC technology, the size of devices is getting smaller and smaller, and the influence of interconnect RC delay on device turn-on speed is increasing, far exceeding the impact of gate delay, so reducing RC interconnect delay has become the focus of attention. On the one hand, people introduce the use of Cu with low resistivity instead of Al with high resistivity to reduce the interconnection resistance, and apply it to the process of 0.25μm and below; on the other hand, people introduce low dielectric constant materials to reduce the number of metal interconnections. capacitance between. In order to solve the problem of Cu diffusion contamination, a thin layer of Cu barrier layer-Ti / TiN or Ta / TaN is deposited before depositing Cu; in order to solve the problem of difficult etc...

AI Technical Summary

Problems solved by technology

[0005] The problem solved by the present invention is that the structure of the etch barrier layer of the low dielectric constant dielectric layer in the prior art is not dense enough, resulting in too low breakdown voltage of the interlayer dielectric layer, causing device reliability problems, and at the same time due to the low dielectric constant The tensile stress in the interlayer dielectric layer of the electric constant will affect the subsequent packaging process and affect the interface adhesion between the interlayer dielectric layer and the interlayer dielectric layer or between the metal Cu and the interlayer dielectric layer

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