Semiconductor component with dual whole metal silicide grids and manufacturing method thereof

A technology of metal silicide and metal silicide layer, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of complicated process and unable to reduce manufacturing cost, and achieve the effect of simplifying process steps and saving costs

Inactive Publication Date: 2008-07-30
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In this way, multiple photolithography and etching processes are required to cover the metal layer o...

Method used

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  • Semiconductor component with dual whole metal silicide grids and manufacturing method thereof
  • Semiconductor component with dual whole metal silicide grids and manufacturing method thereof
  • Semiconductor component with dual whole metal silicide grids and manufacturing method thereof

Examples

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Effect test

no. 1 example

[0108] Figure 1A to Figure 1D It is a process cross-sectional view illustrating a manufacturing method of a semiconductor device with double full metal silicide gates according to the first embodiment of the present invention.

[0109] Please refer to Figure 1A , first provide a substrate 100 . The substrate 100 includes a silicon substrate, such as an N-type silicon substrate or a P-type silicon substrate. Certainly, the substrate 100 may also be a substrate with silicon on an insulating layer or the like.

[0110] A transistor 102 and a transistor 104 have been formed on the substrate 100 . The transistor 102 and the transistor 104 are isolated by, for example, an element isolation structure 106 . The device isolation structure 106 is, for example, a shallow trench isolation structure or a field oxide layer.

[0111] The transistor 102 is composed of, for example, a gate dielectric layer 108 , a gate 110 , a cap layer 112 , a spacer 114 and a source / drain 116 .

[011...

no. 2 example

[0143] Figure 2A to Figure 2D It is a process cross-sectional view illustrating a method for manufacturing a semiconductor device with double full metal silicide gates according to the second embodiment of the present invention. The second embodiment is a modified example of the first embodiment. In the second embodiment, components that are the same as those in the first embodiment are given the same reference numerals, and description thereof will be omitted.

[0144] Please refer to Figure 2A , first provide a substrate 100 . The substrate 100 includes a silicon substrate. A transistor 102 and a transistor 104 have been formed on the substrate 100 . The transistor 102 and the transistor 104 are isolated by, for example, an element isolation structure 106 . The transistor 102 is composed of, for example, a gate dielectric layer 108 , a gate 110 , a cap layer 112 , a spacer 114 and a source / drain 116 . The transistor 104 is composed of, for example, a gate dielectric l...

no. 3 example

[0156] Figure 3A to Figure 3D It is a process cross-sectional view illustrating a method for manufacturing a semiconductor device with double all-metal silicide gates according to a third embodiment of the present invention.

[0157] Please refer to Figure 3A , first provide the substrate 200 . The substrate 200 includes a silicon substrate, such as an N-type silicon substrate or a P-type silicon substrate. Of course, the substrate 200 may also be a substrate with silicon on an insulating layer or the like.

[0158] A transistor 202 and a transistor 204 have been formed on the substrate 200 . The transistor 202 and the transistor 204 are isolated by, for example, an element isolation structure 206 . The device isolation structure 206 is, for example, a shallow trench isolation structure or a field oxide layer.

[0159]The transistor 202 is composed of, for example, a gate dielectric layer 208 , a gate 210 , a spacer 214 and a source / drain 216 . The transistor 204 is co...

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Abstract

The invention discloses a semiconductor element with full-metal-silicide dual-gate, which comprises a first transistor, a second transistor, a dielectric layer and an interlayer insulation layer. The first transistor is arranged on a substrate and includes a first metal silicide gate and a first source/drain. The second transistor is arranged on the substrate and includes a second metal silicide gate and a second source/drain. The material of the first metal silicide gate is different from that of the second metal silicide gate. The first metal silicide gate and the second metal silicide gate are produced in the same metal silicidation technology. The dielectric layer entirely covers the first and the second transistors, and the interlayer insulation layer is arranged on the dielectric layer.

Description

technical field [0001] The present invention relates to a semiconductor element and its manufacturing method, and in particular to a semiconductor element with double full metal silicide gates and its manufacturing method. Background technique [0002] With the increasing integration of integrated circuits, the size of semiconductor elements is also shrinking. When the size of Metal Oxide Semiconductor (MOS) transistors shrinks, the channel length must also shrink accordingly. However, the channel size of MOS transistors cannot be scaled down without limit. When the length of the channel is reduced to a certain extent, various problems will occur due to the decrease of the channel length. This phenomenon is called the short channel effect. In addition to the so-called short channel effect, which will cause the initial voltage (Vt) of the element to drop and the control of the gate voltage (Vg) to the MOS transistor, another phenomenon of breakdown effect will also occur wi...

Claims

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Application Information

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IPC IPC(8): H01L27/02H01L27/092H01L27/12H01L21/82H01L21/8238H01L21/84
Inventor 林经祥许加融程立伟孟宪樑魏铭德许哲华
Owner UNITED MICROELECTRONICS CORP
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