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Method for directly preparing pentacene thin film transistor on SiO2 dielectric layer

A thin film transistor and dielectric layer technology is applied in the field of preparation of pentacene thin film transistors, and can solve problems such as human body and environmental hazards.

Inactive Publication Date: 2010-12-22
THE NAT CENT FOR NANOSCI & TECH NCNST OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] Currently, based on SiO 2 - The carrier mobility of OTS pentacene organic thin film transistor can reach 1cm 2 V -1 the s -1 Above, but this kind of method needs to involve the preparation process of relatively complex single-molecule self-assembly layer, and many toxic reagents such as toluene, chloroform, etc. are used in the process of processing, which have potential hazards to human body and environment

Method used

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  • Method for directly preparing pentacene thin film transistor on SiO2 dielectric layer
  • Method for directly preparing pentacene thin film transistor on SiO2 dielectric layer
  • Method for directly preparing pentacene thin film transistor on SiO2 dielectric layer

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Embodiment 1

[0033] refer to figure 1 .First make a gate electrode on the substrate. In this embodiment, an n-type heavily doped silicon wafer is used as the substrate and the gate at the same time; SiO 2 The dielectric layer is thermally oxidized SiO 2 Dielectric layer, the thickness can be 100-500nm; SiO 2 The cleaning of the surface of the dielectric layer is: ultrasonic cleaning in ammonia solution, wherein the concentration of ammonia solution is 13wt%, and the SiO of this embodiment before and after ammonia treatment is tested by AFM.2 The roughness of the surface of the dielectric layer did not change; the contact angle test showed that the contact angle became smaller after treatment; 2 The pentacene thin film is prepared on the dielectric layer by vacuum evaporation, the deposition rate is 0.001-0.04nm / s, and the vacuum degree is 1×10 -5 mbar~1×10 -7 mbar, the substrate temperature is from room temperature to 60°C, and the thickness is 30-100nm; then prepare the source electrod...

Embodiment 2

[0040] refer to figure 1 .First make the gate electrode on the substrate. In this embodiment, an n-type heavily doped silicon wafer is used as the substrate and the gate at the same time; the dielectric layer is made of thermally oxidized SiO 2 The dielectric layer has a thickness of about 250nm; the method for cleaning the surface of the dielectric layer is: ultrasonic cleaning in ammonia solution, wherein the concentration of ammonia solution is 5wt%; then SiO after surface treatment 2 On the dielectric layer, the pentacene thin film is prepared by vacuum evaporation, the deposition rate is 0.001-0.04nm / s, and the vacuum degree is 1×10 -5 mbar-1×10 -7 mbar, the substrate temperature is from room temperature to 60°C, and the thickness is 30-100nm; then prepare the source electrode and drain electrode on the pentacene film, and the material used for the source and drain electrodes can be Au, Pt, Ag or Al;

Embodiment 3

[0042] refer to figure 1 . The substrate is made of ITO (indium tin oxide) glass; the gate electrode is Au with a thickness of 150nm; SiO 2 The insulating layer is prepared by PECVD method with a thickness of 200nm; SiO 2 The method for cleaning the surface of the dielectric layer is: ultrasonic cleaning in ammonia solution, wherein the concentration of ammonia solution is 29wt%; 2 On the insulating layer, the deposition rate is 0.001~0.04nm / s, and the vacuum degree is 1×10 -5 mbar~1×10 -7 mbar, the substrate temperature is from room temperature to 60°C, and the thickness is 30-100nm; then prepare the source electrode and the drain electrode on the pentacene film, and the material used for the source and drain electrodes can be Au, Pt, Ag or Al; Embodiments related to the invention may also be varied. In addition to silicon wafers, the substrate can also be ITO (indium tin oxide) glass, flexible substrates such as PS (polystyrene), PI (polyimide), PMMA (polymethyl methacr...

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Abstract

A method for directly preparing a pentacene thin film transistor on an SiO2 dielectric layer comprises the following steps: preparing a gate electrode on a substrate layer; preparing the SiO2 dielectric layer on the gate electrode; preparing a pentacene thin film on the SiO2 dielectric layer; and preparing a source electrode and a drain electrode respectively on the pentacene thin film. The preparation of the pentacene thin film on the SiO2 dielectric layer comprises the following steps: firstly, performing ultrasonic cleaning on the SiO2 dielectric layer by 5 weight percent to 29 weight percent ammonia water solution; and secondly, performing deposition and evaporation on the pentacene thin film on the SiO2 dielectric layer subjected to the ultrasonic cleaning by a vacuum evaporation method, wherein the deposition rate is 0.001 to 0.04 nm / s, the vacuum degree is 1*10<-5>mbar to 1*10<-7>mbar, the temperature is between the room temperature and 60 DEG C and the thickness of the deposited pentacene thin film is 30 to 100 nm. The method is simple, safe and environment-friendly and can obtain the transistor with high mobility.

Description

technical field [0001] The invention relates to a preparation method of a pentacene thin film transistor, in particular to a method directly on SiO 2 Method for preparing pentacene thin film transistors on dielectric layer; the mobility of the pentacene thin film transistors can be as high as 1 cm 2 V -1 the s -1 . Background technique [0002] Organic electronic devices can be prepared by methods such as vacuum coating, solution spin coating, inkjet printing, and pattern imprinting. Compatible with substrates, can be processed at room temperature, and can be mass-produced in large areas. When large coverage area, mechanical elasticity (flexibility), low-temperature processing, and especially low cost are required, organic electronic devices are expected to meet the needs of industrialization of low-end electronics, thus attracting great research interest in recent years. Organic thin film transistors are the core components of organic electronic devices, and its import...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L51/40
Inventor 祁琼江潮余爱芳
Owner THE NAT CENT FOR NANOSCI & TECH NCNST OF CHINA