Semiconductor device and method for manufacturing same with stress memorization technology process

Abstract

The invention discloses a method for manufacturing a semiconductor device with an SMT (Stress Memorization Technology) process, comprising the following steps of: forming a gate oxide layer and a grid electrode on a semiconductor substrate; depositing a side wall spacer oxide layer and a side wall silicon nitride layer, and etching the side wall silicon nitride layer; forming a PR (Photoresist) layer on a PMOS (P-channel Metal Oxide Semiconductor) region, and carrying out N<+> ion implantation; removing the side wall oxide layer on an NMOS (N-channel Metal Oxide Semiconductor) region with the PR layer as a mask; removing the PR layer of the PMOS region; forming the PR layer on the NMOS region, carrying out N<+> ion implantation, and removing the PR layer on the NMOS region; forming a buffer oxide layer and a high stress silicon nitride layer; removing the high stress silicon nitride layer on the PMOS region; carrying out a spike annealing process; and removing the high stress silicon nitride layer on the NMOS region. The invention also discloses the semiconductor device. Through adopting the semiconductor device and the method provided by the invention, the electric property of the semiconductor can be improved, the yield of the semiconductor device can be enhanced and the manufacturing cost can be reduced.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device and a method for manufacturing the semiconductor device using a Stress Memorization Technology (SMT, Stress Memorization Technology) process. Background technique [0002] In the existing semiconductor manufacturing process, a stress memory technology (SMT, StressMemorization Technology) process is introduced, which is used after the source / drain (S / D) ion implantation step to induce stress in the metal oxide semiconductor field The channel region of the effect transistor (MOSFET), thereby improving the electrical characteristics of the manufactured components. [0003] In the traditional SMT process, the deposition stress layer and S / D annealing process are usually used to induce stress in the substrate, that is, the polysilicon gate located under the stress capping layer is made recrystallization, thereby improving the electrical performance of...

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Problems solved by technology

However, since the thickness of the buffer oxide layer on the PMOS region is relatively thin, and during the above SAB layer etching process, the etching amount of the NMOS region and the PMOS region is the same, in order to ensure that the SAB on the NMOS region is completely removed Layer, over-etching will inevitably occur in the PMOS region, forming a large pit (divot), which will adversely affect the electrical characteristics of the PMOS semiconductor device.

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