Integrated circuit element and forming method of bumping block structure

Abstract

The invention provides an integrated circuit element and a forming method of a bumping block structure. The integrated circuit element comprises a semiconductor substrate, a bumping block metal layer disposed on the semiconductor substrate, a copper column which is disposed on the bumping block lower metal layer and has a side wall surface and an upper surface, and a protection layer which is disposed on the side wall surface and the upper surface of the copper column. The protection layer is a nickel-containing layer, including phosphor with content being less than 0.01 weight%. The invention provides a copper column bumping block, having a side wall protection layer formed by an electrolytic metal layer. The electrolytic metal layer is an electrolytic nickel layer, an electrolytic gold layer, an electrolytic copper layer or an electrolytic silver layer, preventing the copper column side wall from oxidation, and increasing the adhesion strength between the copper column side wall and the bottom filler materials formed afterwards. The bumping block can prevent stress to be concentrated on one point, resolving the problem that the bumping blocks are peeled off or delaminated from the copper column side wall.

Description

technical field [0001] The present invention relates to the manufacture of integrated circuits, and more particularly to bump structures for integrated circuit components. Background technique [0002] Modern integrated circuits are formed of millions of active elements, such as transistors and capacitors, that are initially isolated from each other but are later interconnected to form a functional circuit. A typical interconnection structure includes horizontal interconnections, such as metal lines (wires), and vertical interconnections, such as vias and contacts. Interconnects are increasingly limiting the density and performance of modern integrated circuits. Influence. The bonding pad is formed on the top of the interconnect structure and is exposed on the surface of the individual chip. The bonding pad can form an electrical connection connecting the chip to the package substrate or other die. The bonding pad Can be used for wire bonding or flip chip bonding. [0003...

AI Technical Summary

Problems solved by technology

Therefore, a sidewall protection layer is needed to avoid copper oxidation, but the traditional method of treating the sidewall of copper pillars requires high manufacturing costs and has interface delamination problems

At present, the chemical immersion tin process (immersion tin process) is used to provide a tin layer on the sidewall of the copper pillar, but there are still problems of manufacturing cost, adhesion between tin and underfill, and solder wetting to the sidewall. It is a challenge for the fine-pitch packaging technology of the new generation of chips

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