FPGA (field-programmable gate array) interconnection structure supporting time division switching
A technology of time-division switching and interconnection structure, applied in the FPGA field, can solve problems such as difficult implementation, slow logic circuit performance, increased chip area and power consumption, etc., to solve scalability problems, solve signal stability, and reduce design complexity sexual effect
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[0059] The solution of the present invention will be further described below in conjunction with the drawings and specific embodiments.
[0060] In order to enable the traditional FPGA structure to support time division switching, several major changes need to be made to the existing traditional FPGA structure:
[0061] The traditional FPGA interconnection resources are composed of CB and SB. The horizontal and vertical wiring channels are connected through the switch box SB, and the input and output of the CLB are connected with each wiring channel through the connection box CB. Both CB and SB in the traditional FPGA structure adopt a spatial exchange structure, and the control switches are all composed of transmission tubes or MUX (multiplexers) composed of transmission tubes, such as Figure 8 Shown.
[0062] The invention converts the interconnection parallel signals in the FPGA into serial signals, which can reduce the number and area of interconnection resources in the FPGA, ...
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