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Method for preparing nanometer structures from top to bottom on surfaces of (110) type silicon chips

A nanostructure and silicon wafer surface technology, which is applied in nanostructure manufacturing, nanotechnology, nanotechnology, etc., can solve the problems of single nanowire structure, high preparation cost, and expensive SOI silicon wafer material, etc., and achieve lattice structure Integrity, good crystal direction alignment and low cost effect

Inactive Publication Date: 2012-04-04
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the SOI silicon wafer material required by this method is expensive, the preparation cost is high, and the preparation object is often only a single nanowire structure. Therefore, the present invention proposes a method for preparing nanostructures from another angle to overcome the existing problems. There are technical shortcomings, and attempts to use lower-cost and more diverse nanostructure preparation methods will have application prospects.

Method used

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  • Method for preparing nanometer structures from top to bottom on surfaces of (110) type silicon chips
  • Method for preparing nanometer structures from top to bottom on surfaces of (110) type silicon chips
  • Method for preparing nanometer structures from top to bottom on surfaces of (110) type silicon chips

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Embodiment 1

[0034] Design of etched windows on (110) silicon wafers for nanowall structures.

[0035] Assume that the x-axis is along the main cutting edge direction of the (110) type silicon wafer. For simplicity, two identical rectangles are arranged side by side along the x-axis direction, as shown in Figure 5 As shown, the length of the nanowall or nanowire is determined by the projected spacing |a| of the two rectangles on the crystal orientation family at 70.52° to the x-axis. value, a is recorded as the effective side length of the rectangle; the width of the nanowall is only affected by the projection spacing b of the two rectangles on the crystal orientation family with an angle of 160.52° to the x-axis, and has nothing to do with the width of each rectangle. Therefore, as long as the positions of several points of the etching window are determined, nanostructures of the required size can be obtained after anisotropic wet etching, with a width of d, a length of l, and an inclu...

Embodiment 2

[0041] (110) Process flow for preparing single crystal silicon nanowires on a silicon wafer ( Figure 6 ).

[0042] a. Take (110) silicon wafers, after cleaning, high-temperature dry oxygen oxidation of 150nm, as a corrosion protection layer;

[0043] b. Design the etching window according to Example 1, get a=17.5um, b=3um, glue photolithography, BOE removes the silicon oxide in the window;

[0044] c. KOH etching, due to the anisotropic wet etching characteristics of (110) silicon wafers, the original two rectangular windows become two hexagonal etching grooves, and a single crystal silicon of crystal direction is formed in the middle of the two etching grooves The wall structure has a rectangular cross section, the height is determined by the corrosion time, the length and width can be determined by the size and position of the corrosion window, and its width is generally controlled at about 100nm.

[0045] d. High temperature oxidation of 150nm, based on the self-limitin...

Embodiment 3

[0048] A method for preparing single crystal silicon nanostructures on (110) type SOI wafers.

[0049] The method for preparing single-crystal silicon nanostructures on (110) type SOI wafers is basically the same as that of Example 1-2, which can be equivalent to that of Example 1-2 occurring on the top silicon or bottom silicon part of (110) type SOI wafers.

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Abstract

The invention relates to a method for preparing nanometer structures from top to bottom on the surfaces of (110) type silicon chips, which belongs to the technical field of nanometer and is characterized in that the anisotropy wet process corrosion characteristics of silicon materials are used for preparing monocrystalline silicon nanometer wall structures or nanometer corner structures with the characteristic dimension being nanometer level on the surfaces of the (110) silicon chips, or a self limitation oxidation process is combined for further preparing the monocrystalline silicon nanometer line structure with the cross section in a reverse triangular shape. The method has the advantages that the process is simple, only the conventional photoetching and the anisotropy wet process corrosion masking manufacture, corrosion and etching processes are adopted, the large-scale manufacture can be realized, and the method belongs to a convenient micro nanometer integrating process technology. The nanometer structure manufactured in the invention can be used for studying the structure properties of the low-dimension monocrystalline silicon materials, including the study of the mechanical property, the thermal property, the electric property and the like, can also be used as sensor function structure components and has the application prospects.

Description

technical field [0001] The invention relates to a method for preparing single crystal silicon nanostructures from top to bottom, more precisely to a method for preparing nanostructures from top to bottom on the surface of a (110) type silicon chip, and belongs to the field of nanotechnology. Background technique [0002] With the development of nanoscience and technology, the nanostructure of materials has been paid more and more attention by researchers because they often show different characteristics from their macroscopic states. Research, so as to better understand various effects at the nanoscale, achieve a deeper understanding of the relationship between the microstructure of materials and their properties, and thus design and manufacture application devices with better performance. [0003] At present, there are two types of methods for preparing nanowires, the first is the bottom-up method (bottom-up) (Xia Y., Yang P., Sun Y., W, Y., Mayers B., Gates B. , Yin Y., K...

Claims

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Application Information

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IPC IPC(8): B82B3/00B82Y40/00
Inventor 金钦华俞骁李铁王跃林
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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