Through silicon via (TSV) filling method

A filling method and technology of through-silicon vias, which are applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as high cost and complex process, and achieve the effect of reducing process difficulty and cost

Inactive Publication Date: 2012-04-11
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The existing second TSV manufacturing method is to make trenches in the front-end process and fill the trenches with silicon dioxide, then expose the silicon dioxide-filled trenches after thinning the silico

Method used

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  • Through silicon via (TSV) filling method
  • Through silicon via (TSV) filling method
  • Through silicon via (TSV) filling method

Examples

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Example Embodiment

[0034] Such as figure 1 Shown is a flowchart of an embodiment of the present invention. Such as Figure 2 to Figure 12 Shown is a schematic cross-sectional view of the silicon wafer during the manufacturing process of the method of the embodiment of the present invention. The method for filling TSV in the embodiment of the present invention includes the following steps:

[0035] Step one, such as figure 2 As shown, a pre-metal dielectric layer 2 is deposited on the silicon wafer 1. Such as image 3 As shown, the through silicon via area is defined by photolithography, the pre-metal dielectric layer 2 and the silicon wafer 1 in the through silicon via area are sequentially etched to form a deep trench or hole 3; the deep trench Or the depth of the hole 3 is 30 micrometers to 250 micrometers, preferably 50 micrometers to 100 micrometers, and the width is 1.5 micrometers to 5 micrometers, most preferably 2 micrometers to 3 micrometers; the metal front dielectric layer 2 is boropho...

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Abstract

The invention discloses a through silicon via (TSV) filling method. The method comprises the following steps: forming a deep groove or hole; depositing an oxide layer on the side walls and bottom of the deep groove or hole; depositing titanium and titanium nitride; depositing a first layer of tungsten; carrying out back etching on the first layer of tungsten to remove the first layer of tungsten outside the deep groove or hole; depositing a layer of titanium nitride; depositing the second layer of tungsten; carrying out back etching on the second layer of tungsten to remove the second layer of tungsten outside the deep groove or hole; if the deep groove or hole is not filled up, repeating deposition and back etching of the second layer of tungsten until the deep groove or hole is filled up; manufacturing front metal interconnects and a front backend process; thinning the back of a silicon wafer; and forming back metal and manufacturing back metal patterns. The method has the following beneficial effects: through combination of a tungsten filling process and a tungsten etching process, the method can be used for realizing the filling of the TSV with high aspect ratio, can be conveniently integrated with the existing integrated circuit process and can be used for processing by utilizing the existing production equipment; and the process difficulty and cost can be reduced.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit manufacturing process method, in particular to a silicon through-hole filling method. Background technique [0002] Through-silicon via technology is an emerging integrated circuit manufacturing process, which is suitable for various performance improvements. It is used in power amplifiers in wireless local area networks and mobile phones, and will greatly improve the frequency characteristics and power characteristics of the circuit. The through-silicon via technology connects the circuit fabricated on the upper surface of the silicon chip to the back of the silicon chip through the metal filled in the through-silicon hole. Combined with the three-dimensional packaging process, the IC layout develops from the traditional two-dimensional side-by-side arrangement to a more advanced three-dimensional stacking, so that components The package is more compact, and the chip lead distance is shorter,...

Claims

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Application Information

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IPC IPC(8): H01L21/768
CPCH01L21/76898
Inventor 彭虎程晓华郁新举
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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