All-wet process for improving integration of double-stress silicon nitride film and structure used in all-wet process

Abstract

The invention relates to the field of manufacture of semiconductor integrated circuits, in particular to an all-wet process for improving the integration of a double-stress silicon nitride film and a structure used in the all-wet process. The invention discloses the all-wet process for improving the integration of the double-stress silicon nitride film and the structure used in the all-wet process, wherein selective etching is realized by adopting a SiN-oxide-SiN-oxide structure and adopting a wet-method etching process in the DSL (Dual Stress Liner) process integration; the damage to a plasma can be avoided; the height of a nitride in an overlap region is reduced by fully utilizing the wet-method etching selectivity of hydrofluoric acid (HF) to an oxide layer and phosphoric acid (HPO) to a nitride layer; and when a first oxide layer and a second oxide layer are opened by using a dry-method etching process, over etching for the oxide layers and the nitride layers (SiN) on the lower layers of the oxide layers is avoided, and thereby the possibility of open circuit of a final circuit is reduced.

Description

technical field [0001] The present invention generally relates to the field of semiconductor integrated circuit manufacturing, and more specifically, the present invention relates to an all-wet process for improving the integration of double-stressed silicon nitride films and structures therein. Background technique [0002] With the increasing integration of semiconductor components, heat dissipation and quantum tunneling have become new problems in chip miniaturization process technology, and strained silicon technology (Stain silicon) adopts a relatively low-cost method that can be applied on a large scale. Increase the distance between silicon atoms, thereby reducing the obstacles to the passage of electrons, that is, reducing the resistance, reducing the heat generation and energy consumption of the device, and improving the operating speed, and this expanded space is where the electrons flow. space, thus effectively reducing the heat dissipation problem and quantum tun...

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Problems solved by technology

[0004] At present, for the above problems, the adjustment of the dry etching process or the consideration of the layout design are mainly used to minimize the impact on the process yield. Although the impact on the process yield can be reduced, the difficulty of process control is correspondingly increased.

The Interuniversity Microelectronics Center (IMEC) proposed a sputtering method to improve the traditional process, such as Figure 2a -c shows the traditional process flow. After the DSL process, ILD and chemical mechanical Polishing (CMP) are performed, and finally etching (Etch) is performed to form through holes; as Figure 3a -c shows that the sputtering process is used. After the DSL process, the sputtering process (Sputter), ILD and CMP are performed, and finally etching (Etch) is used to form through holes. Although it can also reduce the impact on the process yield, there are Significant risk of plasma damage

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