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Image sensor with insulated buried layer and preparation method thereof

An image sensor and insulating buried layer technology, applied in the field of semiconductors, can solve the problems of poor radiation resistance, reduce image signal-to-noise ratio and dynamic range, reduce light absorption rate, etc., to improve the ability to resist high-energy particle radiation and high light absorption efficiency. , the effect of low power consumption

Active Publication Date: 2012-07-04
重庆子丘软件有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0011] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide an image sensor with an insulating buried layer and its preparation method, which is used to solve the problem that the poor radiation resistance of the image sensor in the prior art reduces the quality of the obtained image. The problem of signal-to-noise ratio and dynamic range, as well as the problem of limited depth of effective photosensitive area and reduced light absorption rate

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  • Image sensor with insulated buried layer and preparation method thereof
  • Image sensor with insulated buried layer and preparation method thereof
  • Image sensor with insulated buried layer and preparation method thereof

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Embodiment 1

[0088] Such as Figure 3a to Figure 3f As shown, the present invention provides a kind of preparation method of the image sensor with insulating buried layer, and this preparation method at least comprises the following steps:

[0089] First perform step 1), providing a first semiconductor substrate 1 and a second semiconductor substrate 2, wherein, as Figure 3a As shown, the first semiconductor substrate 1 includes: a first supporting substrate 11, a first insulating buried layer 12 located on the surface of the first supporting substrate 11, and a first insulating buried layer 12 located on the surface of the first insulating buried layer 12. The first top semiconductor layer 13 on the top layer; the second semiconductor substrate 2 is a common semiconductor substrate or a semiconductor substrate with an insulating buried layer. In the first embodiment, as Figure 3b As shown, the second semiconductor substrate 2 is a semiconductor substrate with an insulating buried layer...

Embodiment 2

[0102] Such as Figures 4a to 4g As shown, the present invention also provides a method for preparing an image sensor with an insulating buried layer, which at least includes the following steps:

[0103] First perform step 1), providing a first semiconductor substrate 1 and a second semiconductor substrate 2, wherein, as Figure 4a As shown, the first semiconductor substrate 1 includes: a first supporting substrate 11, a first insulating buried layer 12 located on the surface of the first supporting substrate 11, and a first insulating buried layer 12 located on the surface of the first insulating buried layer 12. The first top semiconductor layer 13 on the top layer; the second semiconductor substrate 2 is a common semiconductor substrate or a semiconductor substrate with an insulating buried layer. In the second embodiment, as Figure 4b As shown, the second semiconductor substrate 2 is a common semiconductor substrate.

[0104] Wherein, the materials of the first support...

Embodiment 3

[0116] Such as Figure 5a and Figure 5b As shown, the present invention provides an image sensor with an insulating buried layer, at least comprising: a supporting substrate 11', an insulating buried layer 12', a top semiconductor layer 3', a pixel readout circuit 4', and an optical sensing device 5' , and the isolation structure 6'.

[0117] The material of the supporting substrate 11' is a common semiconductor substrate material, including at least one of silicon, germanium, silicon germanium, and sapphire.

[0118] The insulating buried layer 12' is located on the surface of the supporting substrate 11', and the insulating buried layer 12' is a single-layer structure or a stacked layer structure, wherein each layer of the single-layer structure or the stacked layer structure The material is at least one of silicon oxide, silicon nitride and silicon oxynitride.

[0119] The top semiconductor layer 3' is located on the surface of the insulating buried layer 12' and has a ...

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Abstract

The invention provides an image sensor with an insulated buried layer and a preparation method thereof. The preparation method comprises the following steps of: providing a first semiconductor substrate and a second semiconductor substrate; defining a first area and a second area on the upper surface of the second semiconductor substrate and arranging a window on the first area; aligning and bonding the upper surface of the first semiconductor substrate and the upper surface of the second semiconductor substrate; thinning the second semiconductor substrate to form a thin film layer and a thick film layer; and finishing the preparation of a pixel read-out circuit and an optical sensing device on the thin film layer and the thick film layer and forming an isolation structure between adjacent devices to finish the preparation of the image sensor with the insulated buried layer. The image sensor has the advantages of good semi-conductor quality and surface quality, higher light adsorption efficiency and excellent performances of high speed, low power consumption and latch-up immunity.

Description

technical field [0001] The invention belongs to the technical field of semiconductors, and relates to an image sensor and a preparation method thereof, in particular to an image sensor with an insulating buried layer and a preparation method thereof. Background technique [0002] SOI (Silicon-On-Insulator, silicon on insulating substrate) technology introduces a buried oxide layer between the top silicon and the back substrate. By forming a semiconductor thin film on an insulator, SOI material has advantages that cannot be compared with traditional bulk silicon materials: it can realize the dielectric isolation of components in integrated circuits, and completely eliminate the parasitic latch effect in bulk silicon CMOS circuits; using this Integrated circuits made of this material also have the advantages of small parasitic capacitance, high integration density, fast speed, simple process, small short channel effect, and are especially suitable for low-voltage and low-power...

Claims

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Application Information

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IPC IPC(8): H01L27/146
Inventor 方娜汪辉陈杰任韬
Owner 重庆子丘软件有限公司