Preparation method of back grid type accumulated mode Si-nanometer wire field effect transistor (NWFET) based on silicon on insulator (SOI)

Abstract

The invention discloses a preparation method of a back grid type accumulated mode silicon-nanometer wire field effect transistor (Si-NWFET) based on a silicon on insulator (SOI). A silicon layer and a silicon germanium layer are formed through etching an SOI substrate, and a fin-shaped active region is formed; silicon nanometer wires are formed in the fin-shaped active region; then, amorphous carbon is deposited on a channel region of the SOI substrate; a grid electrode is formed in the grid electrode channel; a semi-alloy process is formed, and amorphous carbon is removed; the deposition of channel isolation media and interlayer isolation media is simultaneously carried out, and an N-channel metal oxide semiconductor field effect transistor (NMOSFET) is formed; then, a P-channel metal oxide semiconductor field effect transistor (PMOSFET) is formed; and finally, an alloy and metal interconnection process is carried out. The preparation method of the back grid type accumulated mode Si-NWFET based on SOI realizes the NMOSFET and PMOSFET structure separation, so the independent process debugging can be realized, the contact hole resistance of the PMOSFET is effectively reduced for improving the PMOSFET performance, and the carrier migration rate is improved.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a preparation method of a gate-last type accumulation mode Si-NWFET based on SOI. Background technique [0002] By reducing the size of transistors, improving the working speed and integration of chips and reducing the power consumption density of chips have always been the goals pursued by the development of the microelectronics industry. For the past four decades, the development of the microelectronics industry has followed Moore's Law. At present, the physical gate length of field effect transistors is close to 20nm, and the gate dielectric is only a few oxygen atomic layers thick. It has been difficult to improve performance by reducing the size of traditional field effect transistors. This is mainly because of the short channel under small size. The channel effect and gate leakage current degrade the switching performance of the transistor. [0003] Nanowir...

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Problems solved by technology

[0005] 1. NMOS and PMOS share the same gate layer, only clamping CMOS structure can be realized, NMOS and PMOS separation structure cannot be realized, and there are a large number of NMOS and PMOS separation structures in actual CMOS circuits;

[0006] 2. NMOS and PMOS share the same gate layer, and it is impossible to adjust the gate work function and gate resistivity for NMOS and PMOS respectively;

[0007] 3. It is difficult to implement source-drain ion implantation for NMOS and PMOS respectively in the process

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