FINFET dynamic random access memory unit and processing method thereof

Abstract

The invention provides a FINFET dynamic random access memory unit and a processing method thereof. The FINFET dynamic random access memory unit comprises a substrate, a body region, a source electrode, a drain electrode, a fin, a source electrode metal layer, a grid dielectric layer, a grid electrode and a passivation layer. The FINFET dynamic random access memory unit provided by the invention stores the produced carriers in the body region at the lower part a transistor, and based on the substrate bias effect of the transistor, by regulating the charges in the body region of the devices, the FINFET dynamic random access memory unit makes the threshold voltage of the devices vary so as to realize the aim of information storage. The FINFET dynamic random access memory unit is simple in principle, can obtain higher speed, cannot damage the charges stored in the body region during the data reading process, and improves the maximum refresh time; and the FINFET dynamic random access memory unit uses the FinFET structure, so that the reading and writing efficiency is improved. The processing method provided by the invention is simple in technology and compatible to the conventional CMOS (Complementary Metal Oxide Semiconductor) technology, and the dynamic random access memory unit formed by the method cannot damage the charges stored in the body region during the reading process and improves the maximum refresh time.

Description

technical field [0001] The invention belongs to the field of basic electrical components and relates to the preparation of semiconductor devices, in particular to a FINFET dynamic random access memory unit and a preparation method thereof. Background technique [0002] As the size of dynamic random access memory (DRAM) cells continues to decrease, the integration level is getting higher and higher. On the one hand, it is becoming more and more difficult to integrate a transistor and a capacitor together. On the other hand, its destructive way of reading and writing to stored information and its short data retention time make the power consumption brought by refreshing continue to increase. Therefore, in recent years, a one-transistor (1T) DRAM cell that does not contain a capacitor has attracted much attention, and the reason can be attributed to the simpler process of this structure compared with the conventional one-transistor-one-capacitor (1T1C) DRAM cell structure. An...

AI Technical Summary

Problems solved by technology

The holes stored in this way are easily collected by the off-state leakage current of the source region 013 and the drain region 014, and at the same time, due to the carrier recombination effect, the stored holes disappear quickly

Limits the data retention time, narrowing its application field

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