High-voltage lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS) device

Abstract

The invention relates to a high-voltage lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS) device, and belongs to the technical field of semiconductor power devices. On the basis of the conventional high-voltage LDMOS device with reduced field layers, the area of first conduction type of semiconductor reduced field layers (3) in the width direction of the device is reduced by increasing the concentration of the first conduction type of semiconductor reduced field layers (3), so that the first conduction type of semiconductor reduced field layers (3) are discontinuous in the width direction of the device, second conduction type of semiconductor charge balance areas (16) are periodically arranged among the first conduction type of semiconductor reduced field layers (3), additional conduction channels are arranged among the discontinuous reduced field layers (3), the area of a current flow path is increased, and a conduction path is relatively short; and the concentration of the second conduction type of semiconductor charge balance areas (16) can be increased, and the on resistance of the device is greatly reduced. Compared with the conventional high-voltage LDMOS device with the reduced field layers, the high-voltage LDMOS device has the advantages that the on resistance of the device is further reduced, the additional space of a chip is not occupied, and the device can be applied to various products in the fields of consumer electronics, display drivers and the like.

Description

Technical field [0001] The invention belongs to the technical field of semiconductor power devices, and relates to a high-voltage lateral double diffused metal oxide semiconductor device (LDMOS). Background technique [0002] Due to its good process compatibility, high-voltage LDMOS (Double-diffused MOSFET) devices are easy to integrate the source, gate, and drain on the surface with low-voltage logic circuits through internal wiring, and are widely used in high-voltage power Integrated circuit. However, the contradiction between the on-resistance of high-voltage LDMOS devices and the device breakdown voltage has always been a technical bottleneck in the design of high-voltage devices. The on-resistance of DMOS devices is R on There is Ron∝BV with device withstand voltage BV 2.3~2.6 When designing high-voltage devices, in order to obtain a high withstand voltage BV, the on-resistance of the device will inevitably increase. In the device design process, the device is often requir...

AI Technical Summary

Problems solved by technology

Its first conductivity type semiconductor drop field layer 3 is located in the second conductivity type semiconductor drift region 2, and the first conductivity type semiconductor drop field layer 3 is a continuous and simple first conductivity type semiconductor material (such as figure 2 As shown), the first conductivity type semiconductor drop field layer 3 can reduce the on-resistance of LDMOS devices to a certain extent, but it still cannot meet the technical requirements of high-voltage LDMOS devices for power integrated circuits that are developing rapidly.

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