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A kind of strain si/strain sige-hbt BiCMOS integrated device and preparation method

An integrated device and device technology, applied in the field of strained Si/strained SiGeHBT device BiCMOS integrated device and preparation, can solve the problems of low mechanical strength, complex preparation process and high cost

Active Publication Date: 2016-02-10
西安电子科技大学重庆集成电路创新研究院
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Although the frequency characteristics of GaAs and InP-based compound devices are superior, their preparation process is more complicated than that of Si, and the cost is high. 2 Such passivation layer and other factors limit its wide application and development.

Method used

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  • A kind of strain si/strain sige-hbt BiCMOS integrated device and preparation method

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0124] Embodiment 1: Preparation of strained Si, strained SiGeHBTBiCMOS integrated devices and circuits with a channel length of 22nm, the specific steps are as follows:

[0125] Step 1. The collector region is prepared separately from the deep groove.

[0126] (1a) Choose the doping concentration as 5×10 14 cm -3 P-type Si wafer as the substrate;

[0127] (1b) Using chemical vapor deposition (CVD), at 600℃, deposit a 300nm thick SiO on the surface of the epitaxial Si layer 2 Layer, lithography buried layer region, implanting N-type impurities into the buried layer region to form an N-type heavily doped buried layer region;

[0128] (1c) Etch off the oxide layer on the surface of the substrate, and use chemical vapor deposition (CVD) to grow an N-type epitaxial Si layer with a thickness of 1.5μm on the upper Si material at 600°C as a set Electric area, the doping concentration of this layer is 1×10 16 cm -3 ;

[0129] (1d) Using chemical vapor deposition (CVD) method, deposit a layer o...

Embodiment 2

[0197] Embodiment 2: Preparation of strained Si, strained SiGeHBTBiCMOS integrated devices and circuits with a channel length of 30nm, the specific steps are as follows:

[0198] Step 1. The collector region is prepared separately from the deep groove.

[0199] (1a) Choose the doping concentration as 1×10 15 cm -3 P-type Si wafer as the substrate;

[0200] (1b) Using chemical vapor deposition (CVD), at 700℃, deposit a 400nm thick SiO on the surface of the epitaxial Si layer 2 Layer, lithography buried layer region, implanting N-type impurities into the buried layer region to form an N-type heavily doped buried layer region;

[0201] (1c) Etch off the oxide layer on the surface of the substrate, and use chemical vapor deposition (CVD) to grow an N-type epitaxial Si layer with a thickness of 1.8μm on the upper Si material at 700°C. Electric area, the doping concentration of this layer is 5×10 16 cm -3 ;

[0202] (1d) Using chemical vapor deposition (CVD) method, deposit a layer of SiO on...

Embodiment 3

[0270] Embodiment 3: Preparation of strained Si, strained SiGeHBTBiCMOS integrated devices and circuits with a channel length of 45nm, the specific steps are as follows:

[0271] Step 1. The collector region is prepared separately from the deep groove.

[0272] (1a) Choose the doping concentration as 5×10 15 cm -3 P-type Si wafer as the substrate;

[0273] (1b) Using chemical vapor deposition (CVD) method, at 800℃, deposit a thickness of 500nm SiO on the epitaxial Si layer surface 2 Layer, lithography buried layer region, implanting N-type impurities into the buried layer region to form an N-type heavily doped buried layer region;

[0274] (1c) Etch off the oxide layer on the surface of the substrate, and use the chemical vapor deposition (CVD) method to grow an N-type epitaxial Si layer with a thickness of 2.5μm on the upper Si material at 800°C as a set Electric area, the doping concentration of this layer is 1×10 17 cm -3 ;

[0275] (1d) Using chemical vapor deposition (CVD) method,...

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Abstract

The invention discloses a strained Si / strained SiGe-HBT BiCMOS integrated device and a preparation method. The preparation method comprises growing an N-type Si epitaxial layer on a substrate to serve as the collector region of the bipolar device, preparing deep trench isolation, and sequentially preparing base polysilicon, a base region, an emitter region and a collector to obtain the SiGe HBT device; preparing the active region of a PMOS (p-channel metal oxide semiconductor) device, and preparing a drain and a gate on the active region of the PMOS device to obtain the vertical-channel PMOS device; preparing the active region of an NMOS (n-channel metal oxide semiconductor) device, and preparing a gate dielectric layer and gate polysilicon on the active region of the NMOS device to obtain the NMOS device; and etching leads by lithography to obtain the strained Si / strained SiGe-HBT BiCMOS integrated device and circuit. According to the invention, the emitter, the base and the collector of the SiGe HBT all keep polysilicon contact, are prepared by self-alignment process and all have a full planar structure; and the prepared strained Si / strained SiGe-HBT BiCMOS integrated device is enhanced in performance by fully utilizing the characteristics of mobility anisotropy of the strained Si material in preparation of the MOS device.

Description

Technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a strained Si / strained SiGeHBT device BiCMOS integrated device and a preparation method. Background technique [0002] Integrated circuits are the cornerstone and core of the economic development of the information society. As the U.S. engineering technology community recently mentioned the fifth electronic technology among the 20 greatest engineering achievements in the world in the 20th century, “from vacuum tubes to semiconductors and integrated circuits, it has become the cornerstone of intelligent work in various industries today.” One of the typical products that best reflects the characteristics of the knowledge economy. At present, the electronic information industry based on integrated circuits has become the world's largest industry. With the development of integrated circuit technology, the clear boundaries between complete machines a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/06H01L21/8249
Inventor 胡辉勇宣荣喜张鹤鸣宋建军王海栋舒斌李妤晨郝跃
Owner 西安电子科技大学重庆集成电路创新研究院