Recessed alignment mark for electron beam overlay on soi and manufacturing method thereof

Abstract

The invention discloses a recessed type alignment mark used for electron beam alignment on SOI (Silicon On Insulator) and a manufacturing method thereof. The manufacturing method concretely comprises the following steps: washing an SOI substrate; coating optical resist on the SOI substrate, and transferring the pattern of the alignment mark to the optical resist with photoetching technology; plating metal films on the surfaces of the SOI substrate and the optical resist; peeling off the metal film on the optical resist; etching silicon and silicon dioxide of the SOI substrate at the metal film so as to obtain the recessed type alignment mark; and removing remaining metal film on the SOI substrate. The manufactured recessed type alignment mark is good in sidewall steep performance; the alignment precision of the recessed type mark on the SOI thin silicon film is improved; and the recessed type alignment mark is compatible with CMOS (Complementary Metal-Oxide-Semiconductor Transistor) technology, and can be applied to the technologies of high-temperature epitaxial growth, high-temperature oxidation and the like without worrying about introduced impurities or deformation and displacement of the mark.

Description

technical field [0001] The invention belongs to the field of micro-nano manufacturing of semiconductor devices, in particular, it relates to a recessed alignment mark and its Production Method. Background technique [0002] Driven by semiconductor industry giants such as Intel and IBM, the size of semiconductor devices is getting smaller and smaller, and the semiconductor micro-nano manufacturing technology with Complementary Metal Oxide Semiconductor (CMOS, Complementary Metal Oxide Semiconductor) technology as the mainstream is currently and will continue to follow the " Moore's Law" development. The development of integrated circuits has reached the current era of extremely large-scale nanotechnology. To further improve the integration and operating speed of chips, the existing bulk silicon materials and processes are approaching their physical limits. In order to further reduce the feature size of integrated circuits, new major breakthroughs must be made in materials a...

AI Technical Summary

Problems solved by technology

However, since the melting point of gold is only 1063°C, if the sample needs to be used in high-temperature thermal oxidation or epitaxial growth processes, metal melting deformation and metal diffusion will occur, and then the cavity for epitaxial growth will be polluted, which will bring very serious consequences.

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