N-channel metal oxide semiconductor (NMOS) component manufacturing method using stress memorization technology

Abstract

The invention discloses a N-channel metal oxide semiconductor (NMOS) component manufacturing method using a stress memorization technology, which, after depositing a barrier layer, before depositing a first silicon nitride layer, implements an ion implantation of nitrogen and a rapid thermal process (RTP) annealing process, to improve the uniformity and density of the barrier layer, so that the comparatively dense barrier layer is formed, and a hydrogen diffusion stopping capacity generated in the process of manufacturing the first silicon nitride layer, thereby inhibiting diffusion of boron ions which are injected in source / drain into a grid medium layer in following steps of depositing the first silicon nitride layer, and spike and laser annealing steps; and later on, the first silicon nitride layer and the barrier layer are removed by a wet-process or dry-process etching. Therefore, the distribution of trapped charges on the surface and in the grid dielectric layer of the NMOS component is not affected in the using process, ad the performance of the manufactured semiconductor component is improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to an NMOS device manufacturing method using a stress memory technology (SMT, Stress Memorization Technique). Background technique [0002] At present, the semiconductor manufacturing industry mainly grows devices on the wafer (wafer) device surface of the silicon substrate. Taking Metal-Oxide Semiconductor Field Effect Transistor (MOS) as an example, the MOS device structure includes active regions, source, drain and gate, wherein the active region is located in the silicon substrate, the gate is located above the active region, and the active regions on both sides of the laminated gate 106 are respectively formed after ion implantation The source electrode and the drain electrode have a conductive channel under the gate, and a gate dielectric layer is arranged between the gate and the conductive channel. According to the type of majority carriers in the conduction chann...

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Problems solved by technology

[0015] Although the above method can improve the gate tensile stress of NMOS devices, it will also cause the negative bias temperature instability (NBTI, Negative Bias Temperature Instability) effect. The NBTI effect refers to the negative gate voltage applied to the MOS at high temperature. The degradation of a series of electrical parameters (the general stress condition is the gate oxide electric field at a constant temperature of 125°C, the source, drain and substrate are grounded), and there will also be problems such as gate leakage current

Part of the reason for these problems is that the charged particles produced in the process of making NMOS devices by SMT will diffuse to the surface and inside of the gate dielectric layer, affecting the distribution of the trapped charges on the surface and inside of the gate dielectric layer during the use of NMOS devices.

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