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Si/CoSi2 substrate material on imaging insulation body and preparing method thereof

A technology of substrate material and insulator, which is applied in the field of Si/CoSi2 substrate material on patterned insulator and its preparation, can solve the problems of increasing the thickness of the top layer silicon, occupying the space of the top layer silicon, increasing the breakdown voltage of the substrate, etc., and achieves simplification Process, reduced thickness, the effect of simple process

Active Publication Date: 2014-12-24
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The traditional SOI substrate includes a back substrate, an insulating layer, and the top layer of silicon on the insulating layer. The manufacture of general SOI bipolar circuits and BiCMOS circuits needs to make a heavily doped buried layer in the traditional SOI top layer of silicon to reduce the Collector resistance and increase the breakdown voltage of the substrate, however, such manufacturing process steps are complicated, and occupy part of the space of the top layer of silicon, increasing the thickness of the top layer of silicon
Moreover, the traditional SOI BICMOS process generally manufactures bipolar circuits and CMOS circuits on the top layer of silicon with the same thickness as the traditional SOI. As a result, the SOI CMOS circuit is difficult to achieve full depletion during operation, which greatly reduces the operating speed of the SOI CMOS circuit and affects the improvement of the operating speed of the BICMOS circuit.

Method used

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  • Si/CoSi2 substrate material on imaging insulation body and preparing method thereof
  • Si/CoSi2 substrate material on imaging insulation body and preparing method thereof
  • Si/CoSi2 substrate material on imaging insulation body and preparing method thereof

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Embodiment 1

[0036] Such as Figure 1 to Figure 11 As shown, the present invention provides a patterned Si / CoSi on insulator 2 The preparation method of substrate material, described preparation method comprises the following steps at least:

[0037] see Figure 1 to Figure 4 , as shown in the figure, step 1) is first carried out to provide a first Si substrate 111, which is a common silicon wafer, and then standard wet chemical treatment is performed on the first Si substrate 111. cleaning method to remove impurity ions and surface defects on the surface, and form a photoresist 112 on the surface of the first Si substrate 111 to be prepared in the MOS device region. The photoresist 112 is a positive photoresist. A Co layer 113 is formed on the surface of the first Si substrate 111 and the photoresist surface 112 by a deposition method in a vacuum environment, and then a Ti layer 114 is deposited on the Co layer 113, and the Co layer 113 The thickness of the Ti layer is 15-30nm, and the ...

Embodiment 2

[0043] see Figure 1 to Figure 11 , as shown in the figure, the patterned Si / CoSi-on-insulator 2 The basic steps of the preparation method of the substrate material are as in Example 1, the photoresist 112 is reversed, the thickness of the Co layer 113 is 15 nm, and the thickness of the Ti layer 114 is 5 nm. The first annealing temperature is 500°C, the second annealing temperature is 800°C, and the third annealing temperature is 400°C.

[0044] see Figure 11 , as shown in the figure, the patterned Si / CoSi-on-insulator 2 The basic structure of the substrate material is as in embodiment 1, wherein the CoSi 2 Layer 115 has a thickness of 30 nm. The thickness of the Si top layer 111 is 20nm.

Embodiment 3

[0046] see Figure 1 to Figure 11 , as shown in the figure, the patterned Si / CoSi-on-insulator 2 The basic steps of the preparation method of the substrate material are as in Example 1, wherein the photoresist 112 is positive resist, the thickness of the Co layer 113 is 30 nm, and the thickness of the Ti layer 114 is 10 nm. The first annealing temperature is 600°C, the second annealing temperature is 900°C, and the third annealing temperature is 600°C.

[0047] see Figure 11 , as shown in the figure, the patterned Si / CoSi-on-insulator 2 The basic structure of the substrate material is as in embodiment 1, wherein the CoSi 2 Layer 115 has a thickness of 150 nm. The thickness of the Si top layer 111 is 200nm.

[0048] In summary, the patterned Si / CoSi on insulator of the present invention 2 Substrate material and its preparation method A patterned metal Co layer is produced by lift-on technology, and then the Co layer is reacted with the Si substrate twice to form CoSi 2 ...

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Abstract

The invention provides a Si / CoSi2 substrate material on an imaging insulation body and a preparing method thereof. The method includes that an imaging metal Co layer is manufactured through lift-on technology, the Co layer and a Si substrate conduct twice reacting to form CoSi2, transferring of the CoSi2 is conducted through an intelligent peeling process, a layer of metal silicide CoSi2 is inserted into a partial region between a BOX layer and top layer silicon of a traditional silicon-on-insulator (SOI) substrate so as to replace a heavy doping buried layer of a collector region in a conventional SOI bipolar transistor, regions in which no CoSi2 is inserted are used for manufacturing metal oxide semiconductor (MOS) devices, and the aims that the thickness of the top layer silicon is reduced, a process is simplified and the like are achieved. The preparing method is simple in process and suitable for large-scale industrial production.

Description

technical field [0001] The invention belongs to the field of semiconductors, in particular to a patterned Si / CoSi on insulator 2 Substrate material and its preparation method. Background technique [0002] BiCMOS is a new generation of high-performance VLSI process after CMOS. CMOS has become the mainstream process of VLSI in 80 years with low power consumption and high density. As the size is gradually reduced, the circuit performance is continuously improved, but when the size drops below 1um, its potential is greatly limited due to carrier velocity saturation and other reasons. The basic idea of ​​integrating CMOS and Bipolar on the same chip is to use CMOS devices as the main unit circuit, and add bipolar devices or circuits where it is required to drive large capacitive loads. High speed, low power consumption. Therefore, BiCMOS circuits not only have the advantages of high integration and low power consumption of CMOS circuits, but also have the advantages of high-...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8249H01L29/06
Inventor 俞文杰张波赵清太狄增峰张苗王曦
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI