Three-dimensional multi-chip laminated module and manufacturing method thereof

Abstract

The invention discloses a three-dimensional multi-chip stacked module and a manufacturing method thereof. The three-dimensional stacked multi-chip module includes a stack of W IC chips, each chip has a patterned conductive layer, and includes a The electrical contact area, in some examples, includes the component circuit on the substrate; the conductors in the stacked chip are aligned with each other, and a plurality of electrical connectors extend along the interior of the stack to contact the connection pads in the conductors, creating a three-dimensional Stacked multi-chip module; electrical connectors can pass through vertical through holes in the electrical contact area; connection pads can be arranged in steps; this stacked multi-chip module can be made with N etching masks, where 2N-1 is less than W, and 2N is greater than or equal to W; these etching masks alternately cover and expose 2n-1 connection pads, where n=1, 2...N.

Description

technical field [0001] The invention relates to a three-dimensional stacked multi-chip (circle) module, in particular to a three-dimensional stacked multi-chip (circle) module made by using TSV technology and a manufacturing method thereof. Background technique [0002] A manufacturing method of a three-dimensional integrated circuit (3DIC) is to vertically stack and bond a plurality of semiconductor chips to produce a single 3DIC. The electrical connection from the external connection pads to the electrical conductors in the 3DIC, and the electrical connection between different conductive layers in the 3DIC can be achieved in various ways. For example, in a method of wire bonding, the edges of adjacent chips can be staggered in steps. In this way, the bonding pads of the chip and the bonding pads on the substrate can be connected with external bonding wires. [0003] Another method of electrically connecting stacked chips, called through-silicon via (TSV), has attracted s...

AI Technical Summary

Problems solved by technology

The advantage of using chip-level stacking is that it is easier to handle, but the cost is relatively high

[0005] Another disadvantage of traditional TSV technology is that the general TSV process requires 11 steps per chip or wafer: TSV photoresist layer deposition, TSV etch, silicon dioxide layer deposition, barrier layer / seed layer Deposition, patterning photoresist, Cu / W layer deposition, photoresist layer removal, chemical mechanical polishing of Cu / W layer, support / handling diebonding, die thinning, and bonding

In addition to the time and expense required to perform these steps, the handling and processing required for individual chips also results in lower yields

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