Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device, which comprises a substrate, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, and a plurality of gate spacer structures on both sides of each gate spacer structure. The plurality of source and drain regions in the substrate, the plurality of gate stack structures include a plurality of first gate stack structures and a plurality of second gate stack structures, wherein the first gate stack structure includes a first gate an insulating layer, a first barrier layer, a first work function adjustment layer, and a resistance adjustment layer, and the second gate stack structure includes a second gate insulating layer, a first barrier layer, a second work function adjustment layer, and a first work function adjustment layer. adjustment layer, and resistance adjustment layer. According to the semiconductor device and its manufacturing method of the present invention, the NMOS work function adjustment layer is selectively deposited first and then the PMOS work function adjustment layer is deposited, which simplifies the PMOS metal gate structure, and can improve the resistance while effectively controlling the work function of the metal gate. Adjust the space filled by the layer, thus effectively reducing the gate resistance.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a CMOS with more effective control of work function and reduced gate resistance and a manufacturing method thereof. Background technique [0002] Starting from the 45nm CMOS integrated circuit process, with the continuous reduction of device feature size, in order to suppress the short channel effect, the equivalent oxide thickness (EOT) of the gate insulating dielectric layer in CMOS devices must be reduced simultaneously. However, due to the low (relative) dielectric constant (for example, about 3.9) of the ultra-thin (eg 10nm) conventional oxide layer or oxynitride layer, the insulation performance is difficult to withstand the relatively high field strength in such ultra-small devices, which will cause serious damage. gate leakage. Therefore, the traditional polysilicon (poly-si) / SiON system is no longer applicable. [0003] In view of this, the i...

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Problems solved by technology

In this way, in the device structure of the PMOS region, the metal gate structure is extremely complex (containing three barrier layers), and under the condition that the feature size-gate length is gradually reduced, especially when the gate length is below 22nm, at this time due to many The structure of the layer barrier layer reduces the space that can be filled by the resistance adjustment layer in the PMOS region, and there are problems that the resistance adjustment layer is small and difficult to effectively reduce the gate resistance, and insufficient filling causes holes to increase the resistivity.

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