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A method for producing a conductive channel

A technology of conductive channel and manufacturing method, which is applied in the direction of semiconductor/solid-state device manufacturing, circuits, electrical components, etc., to achieve the effect of improving mobility and increasing stress

Active Publication Date: 2014-03-26
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, how to improve the performance of MOS devices has always been a technical difficulty

Method used

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  • A method for producing a conductive channel
  • A method for producing a conductive channel
  • A method for producing a conductive channel

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Experimental program
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specific Embodiment 1

[0026] combine Figure 2a ~ 2g Description such as figure 2 Shown specific embodiment of the present invention one is with MOS device conduction channel fabrication technological process, and its concrete steps are as follows:

[0027] Step 21, Figure 2a It is a schematic cross-sectional structure diagram of step 21 of making the conductive channel of the MOS device of the present invention, such as Figure 2a As shown, a polysilicon layer is deposited on the wafer device surface of a silicon substrate 200 , and the polysilicon layer is etched after the first photolithography to form a dummy gate (dummy gate) 201 .

[0028] In this step, a p-type (or n-type) silicon substrate 200 is provided. The STI structure (not shown in the figure) and the active region have been fabricated in the silicon substrate 200, and the MOS is subsequently fabricated on the active region. The device structure, the step of depositing a polysilicon layer on the device surface of the silicon subs...

specific Embodiment 2

[0045] combine Figure 3a-3g Illustrate the present invention as image 3 The specific steps of fabrication of the FinFET conductive channel shown are as follows:

[0046] Step 31, Figure 3a It is a schematic cross-sectional structure diagram along the length direction of the fin in Step 31 of making the conductive channel of the FinnFET according to the present invention. As shown in FIG. 10 , the fin 301 is formed on the surface of the semiconductor substrate 300 .

[0047] In this step, the semiconductor substrate 300 provided is bulk silicon or silicon-on-insulator SOI; Fins 301 are formed by etching the silicon layer. Among them, photolithography refers to: coating photoresist on the Si layer, and patterning the photoresist to form a photolithographic pattern (not shown in the figure) through exposure and development processes; etching the Si layer by dry etching, Using the photolithographic pattern as a mask, use anisotropic reactive ion etching (RIE) or high-densit...

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Abstract

The application discloses a method for producing a conductive channel. A [sigma]-type conductive channel extended to a source electrode and a drain electrode is formed on a semiconductor substrate. On one hand, silicon germanide or silicon carbide grows in the [sigma]-type conductive channel multistep epitaxial in a multistep epitaxial manner. On the other hand, the dosage concentration of non-silicon element on the edge of the [sigma]-type conductive channel is less than that on the center of the [sigma]-type conductive channel. Thus, by means of gradually-varied dosage concentration of non-silicon element, lattice mismatch at interfaces between the source and drain electrodes and the conductive channel is decreased to form heterojunctions, stress in the conductive channel is increased, and migration rates of charge carriers of the source and drain electrodes are increased.

Description

technical field [0001] The invention relates to the manufacturing technology of semiconductor devices, in particular to a method for manufacturing a conductive channel. Background technique [0002] At present, the semiconductor manufacturing industry mainly grows devices on the wafer (wafer) device surface of the silicon substrate, for example, Metal-Oxide Semiconductor Field Effect Transistor (MOS), and the MOS device structure includes active regions, source, drain and gate, wherein the active region is located in the semiconductor silicon substrate, the gate is located above the active region, and ion implantation is performed in the active regions on both sides of the gate to form the source and drain, with a conductive channel under the gate, and a gate dielectric layer between the gate and the conductive channel, such as figure 1 shown. According to different types of ion implantation, hole type metal oxide semiconductor field effect transistor (PMOS) and electron t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336
CPCH01L29/66568
Inventor 赵猛
Owner SEMICON MFG INT (SHANGHAI) CORP