Input-driven domino circuit design

Abstract

The invention relates to input-driven domino circuit design. A domino circuit is structurally optimized, transistors of a clock are removed, and a clock signal is replaced by combined input data, so that dynamic power consumption can be reduced, the number of transistors of the circuit is decreased, the working time is shortened, the circuit performance is improved, and the layout area of the circuit is reduced. According to the input-driven domino circuit design, the problem of high power consumption caused by the clock is effectively solved, and the clock signal is removed from the circuit and is replaced by the combined input data, so that the turn-on and turn-off frequency of the transistors can be greatly reduced, the dynamic power consumption of the circuit is effectively reduced, and the layout area of a chip is reduced.

Description

Technical field [0001] The invention relates to a domino circuit, belonging to the field of circuit design, in particular to an input-driven domino circuit design. Background technique [0002] At present, the level of integrated circuit technology is increasing, the process size of semiconductor devices is continuously reduced, the degree of chip integration is continuously improved, and the functional units that can be integrated on a single chip are continuously increasing, resulting in higher and higher total power consumption of the circuit. In addition, battery-powered portable electronic products are increasingly widely used, such as handheld computers, mobile phones, and notebook computers. The battery power supply time is shortened and the circuit thermal effect is becoming more and more serious. The circuit power consumption has become a key problem in circuit design, especially the power consumption problem of VLSI design has been unavoidable. After the integrated cir...

AI Technical Summary

Problems solved by technology

The output is conditionally discharged according to the input value and the situation of the pull-down topology; in the working process, the clock power consumption of the domino is very large, especially because the node 1 will be frequently charged and discharged; many methods to reduce the power consumption of the domino circuit have been proposed , such as multi-supply voltage technology, gated clock technology, P-type network technology, charge self-compensation technology and narrow pulse technology, etc. However, for domino circuits, a large amount of power consumption is consumed in the clock network, and these technologies do not target the clock signal Optimized for very limited suppression of power consumption

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