Semiconductor device and forming method thereof

Abstract

The invention discloses a semiconductor device and a forming method thereof. The semiconductor device comprises a semiconductor substrate, a first gate structure, a second gate structure, a second dielectric layer and a first conductive plug, wherein the semiconductor substrate comprises a first region and a second region near to each other; the first gate structure is located on the surface of the semiconductor substrate in the first region, and the first gate structure comprises a first high K gate dielectric layer, a first work function layer located on the surface of the first high K gate dielectric layer and a first gate electrode layer located on the surface of the first work function layer; the second gate structure is located on the surface of the semiconductor substrate in the second region, and the second gate structure comprises a second high K gate dielectric layer, a second work function layer located on the surface of the second high K gate dielectric layer and a second gate electrode layer located on the surface of the second work function layer; the second dielectric layer is located on the surface of the first gate structure and the second gate structure, and the second dielectric layer is internally provided with a contact through hole exposed out of part of the first gate structure and part of the second gate structure; and the first conductive plug is formed and located in the contact through hole. Performances of the semiconductor device are good.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a forming method thereof. Background technique [0002] Complementary Metal-Oxide-Semiconductor (CMOS) has become a commonly used semiconductor device in integrated circuits. The CMOS transistors include: P-type metal oxide semiconductor transistors (PMOS) and N-type metal oxide semiconductor transistors (NMOS). In the prior art, in order to control the short channel effect while reducing the gate size, high-K dielectric materials are used to replace conventional silicon oxide and other materials to form gate dielectric layers, and metal materials are used to replace conventional polysilicon and other materials to form gate electrode layers; in addition , in order to adjust the threshold voltage of the PMOS tube and the NMOS tube, the existing technology will form a work function layer (work function layer) on the surface of the gat...

AI Technical Summary

Problems solved by technology

[0006] However, in the prior art, the common gate electrode CMOS transistor with high K gate dielectric layer and metal gate electrode has poor performance

Images