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EEPROM (Electrically Erasable Programmable Read Only Memory) and memory array thereof

A storage array and storage unit technology, applied in the field of memory, can solve the problems of large EEPROM size, etc., and achieve the effect of increasing the area of ​​the active area, reducing the volume, and improving the performance

Inactive Publication Date: 2014-05-21
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The present invention solves the problem that the existing EEPROM has a large volume

Method used

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  • EEPROM (Electrically Erasable Programmable Read Only Memory) and memory array thereof
  • EEPROM (Electrically Erasable Programmable Read Only Memory) and memory array thereof
  • EEPROM (Electrically Erasable Programmable Read Only Memory) and memory array thereof

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Embodiment Construction

[0024] As described in the background technology, in order to guarantee the performance of EEPROM, it is no longer possible to figure 1 The memory cell structures shown are scaled down in whole or in part. for figure 1 The EEPROM memory array formed by the memory cells shown in the prior art usually uses hot electron injection (HCI, Hot Carrier Injection) for programming and erasing, that is, it is necessary to apply a high voltage to the source line SL connected to the source electrode 11. Voltage. Since the source lines SL need to withstand a relatively high voltage, the manufacturing process determines that the source lines SL need to be arranged in a row direction, that is, the sources of the memory cells in the same row are connected to the same source line.

[0025] The technical solution of the present invention provides an EEPROM storage array. By changing the operation mode of the EEPROM storage array, it is possible to connect the sources of the storage cells locat...

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Abstract

The invention relates to an EEPROM (Electrically Erasable Programmable Read Only Memory) and a memory array thereof. The memory array comprises at least one byte memory area, wherein each byte memory area comprises M word lines which are arranged according to the row direction, 8 bit lines which are arranged according to the column direction, 8 source lines which are arranged according to the column direction and memory cells which are arranged in a matrix with M rows and 8 columns, the memory cells comprise grid electrodes, drain electrodes and source electrodes, and M is a positive integer; the grid electrodes of the memory cells in the same row are connected to the same word line, the drain electrodes of the memory cells in the same column are connected to the same bit line, and the source electrodes of the memory cells in the same column are connected to the same source line. According to the EEPROM and the memory array thereof, provided by the technical scheme of the invention, the source electrodes of the memory cells in the same column are connected to the same source line, and the source lines are arranged according to the column direction, so that the volume of the EEPROM is shortened.

Description

technical field [0001] The invention relates to the technical field of memory, in particular to an EEPROM and a storage array thereof. Background technique [0002] Electrically Erasable Programmable Read-Only Memory (EEPROM, Electrically Erasable Programmable Read-Only Memory) is a semiconductor storage device with byte (Byte) as the minimum modification unit, which can be electronically rewritten multiple times. Compared with Erasable Programmable Read-Only Memory (EPROM, Erasable Programmable Read-Only Memory), EEPROM does not need to be irradiated with ultraviolet light or removed. It can use a specific voltage to erase the information on the chip for writing. Enter new data. Due to the excellent performance of EEPROM and the convenience of online operation, it is widely used in BIOS chips and flash memory chips that need to be frequently erased, and gradually replaces some random access memory (RAM, Random Access Memory) chips that require power-off retention. , and e...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/06
CPCG11C16/0416G11C16/10G11C16/24G11C16/08G11C16/14G11C16/26
Inventor 顾靖孔蔚然张博张雄李冰寒
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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