Low-power-consumption thin back gate graphene field effect transistor manufacturing method

Abstract

The invention discloses a low-power-consumption thin back gate graphene field effect transistor manufacturing method. A SiO2 dielectric layer is grown on the surface of an n-type Si substrate through heat, the SiO2 dielectric layer is subjected to photoetching, the SiO2 dielectric layer is etched with reactive ions after development, grooves are formed, graphene is transferred to the etched SiO2 dielectric layer, graphene channels are formed, TiW alloy with the thickness of 5 nm and Au with the thickness of 100 nm are sequentially arranged on the surfaces of the graphene channels in a sputtering mode, then, photoetching is performed, the TiW / Au is corroded to form a linear Au connecting wire and an Au electrode plate after development, a source electrode and a drain electrode are formed, and the purpose of low power consumption and the purpose of high performance are effectively achieved.

Description

technical field [0001] The invention belongs to the technical field of nanoelectronic components and relates to a method for preparing a low-power consumption thin back-gate graphene field-effect transistor. Background technique [0002] Field-effect transistors (FETs) are the most important devices in very large-scale integrated circuits such as microprocessors and semiconductor memories. FET through the gate-source voltage ( V gs ) to control the conductivity of the channel, so as to control the output current ( I ds ) size purposes. As a high-speed response device, FET must respond quickly to changing gate-source voltage, so it needs to have a small gate and a conductive channel with high carrier mobility. [0003] In 2004, condensed matter physicists discovered a graphene that is only a few atomic layers thick at room temperature. This material is composed of carbon atoms with sp 2 The hybrid orbitals form a hexagonal planar film with a honeycomb lattice, and its ...

AI Technical Summary

Problems solved by technology

According to Moore's Law, every 18 to 24 months, the transistor density of integrated circuits doubles and the operating frequency doubles, but the power consumption also doubles, which has become the biggest bottleneck of Moore's Law, so the design and manufacture of ultra-low power consumption Nanoelectronic components are an urgent problem to be solved today

At present, the common back-gate graphene field-effect transistors are all based on 300nm thick SiO 2 As a gate dielectric layer, its input voltage is relatively large, and its power consumption is relatively large

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