Router structure capable of sharing and self-configuring cache

Abstract

The invention belongs to the field of reliability on-chip network design, in particular to a router structure capable of sharing and self-configuring a cache applied to an on-chip network. The router structure comprises cache units, routing computation units, a data exchange switch, an arbiter, an adjacent channel status monitor and a local channel status monitor. According to the router structure, the adjacent channel status monitor and the local channel status monitor are added in the conventional router structure, so that the status of a router channel in the local on-chip network can be effectively monitored, and the routing computation unit is capable of figuring out a more reasonable routing path according to the real-time channel status information, thus the local congestion probability of the on-chip network is reduced, the throughput rate of the on-chip network is improved, and a delay to reach a target node of data of the on-chip network is reduced. Each of cache units of an eastern port, a southern port, a western port and a northern port contains a cache formed by three first input-first output queues, and two virtual data channels are formed, so that sharing of the caches is implemented in a self-configuration manner, and self-adaptability of data routing is effectively increased.

Description

technical field [0001] The invention belongs to the technical field of reliable on-chip network design, and in particular relates to a shared and self-configurable cache router structure applied to an on-chip network. Background technique [0002] With the continuous increase of chip scale and the continuous development of production technology, the disadvantages of the bus-based SoC architecture are becoming more and more obvious. 1) The throughput and bandwidth are limited, which makes the overall communication efficiency low; 2) The bus energy consumption is large and the energy utilization efficiency is low. , and the signal delay increases; 3) As the integration level continues to increase, the signal crosstalk between chip lines and different metal layers becomes more and more serious; 4) Global synchronization is required; 5) The scalability is poor. These shortcomings make SoC unable to meet the requirements of ultra-deep sub-micron VLSI systems for throughput, delay...

AI Technical Summary

Problems solved by technology

[0003] At the same time, in a typical fault-tolerant routing system, in many specific applications, the communication mode presents a mode of local high load and global low load, so that many router cache units are in an idle state, but some are in a high-load busy state , this kind of load imbalance leads to the limitation of the high throughput characteristics of the NoC system, so there is an urgent need for an anti-congestion routing system that can relieve this limitation

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