CMOS image sensor with high pixel and high frame rate and image acquisition method

Abstract

The invention relates to a CMOS image sensor with high pixel and high frame rate and an image acquisition method, comprising a pixel array part (101), an incremental ΣΔADC array part (102), a digital correlation double sampling part (103) and a buffer memory which are sequentially connected The part (104) also includes a row decoding unit part (105), and the signal output terminal of the row decoding unit part (105) is connected to the control terminal of the pixel array part (101), and also includes a column readout control circuit (106), The signal output terminal of the column readout control circuit (106) is connected to the control terminal of the buffer memory part, and the incremental ΣΔADC array part (102) is connected with a voltage buffer (107) and a clock delay and driving circuit (108).

Description

technical field [0001] The invention relates to a CMOS image sensor with high pixel and high frame rate and an image acquisition method. Background technique [0002] The image sensor is the core component of digital image acquisition. It uses the photoelectric conversion effect of semiconductor materials to realize the capture of optical signals, conversion to electrical signals and post-processing. In the past two decades, charge-coupled device (CCD) image sensors have been dominating the image sensor market due to their advantages such as low fixed-pattern noise, low dark current, high sensitivity, and high quantum efficiency. However, compared with CCD image sensors, CMOS image sensors can adopt mature CMOS process technology, and can integrate sensitive cell arrays, analog, and digital systems on a single chip, which has the advantages of low power consumption, low cost, and high integration. Therefore, the current CMOS image sensor has occupied most of the low-end mar...

AI Technical Summary

Problems solved by technology

At present, column-parallel ADCs generally use single-slope ADCs or cyclic ADCs. However, single-slope ADCs need 2 N clock cycles, limiting the speed increase; cyclic ADCs require very accurate amplifiers, resulting in higher power consumption

Sigma-Selta (ΣΔ) is a high-precision ADC commonly used in audio and video signal fields, but its complex timing and high power consumption limit its application in CMOS image sensors

In recent years, a ΣΔ ADC with a simple Class-C structure inverter as an operational amplifier has appeared, which has achieved lower power consumption, but the simple Class-C structure inverter used is seriously affected by the process. The linear gain range is small, which severely limits the gain and bandwidth of the amplifier, and also limits the further improvement of the pixel array and frame rate in the CMOS image sensor it is applied to

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