Self-gating resistance-variable memory unit and preparation method thereof

Abstract

The invention discloses a self-gating resistance-variable memory unit and a preparation method thereof and belongs to the technical field of memories. The self-gating resistance-variable memory unit comprises a stack structure, a vertical trench, an M8XY6 gating layer, a resistance transition layer and upper conductive electrodes, wherein the stack structure contains a plurality of layers of lower conductive electrodes; the vertical trench is formed by etching the stack structure; the M8XY6 gating layer is formed on the inner wall of the vertical trench and at the bottom of the vertical trench; the resistance transition layer is formed on the surface of the M8XY6 gating layer; the upper conductive electrodes are formed on the surface of the resistance transition layer and the vertical trench is filled with the upper conductive electrodes. The self-gating resistance-variable memory unit and the preparation method thereof have the benefits that based on a resistance-variable memory with a self-gating function taken as the memory unit, a self selection function can be realized by means of the features of nonlinear variation of own resistance of the memory unit along with voltage without relying on a gated transistor and a diode; the structure is simple, the integration is easy, the density is high, the cost is low, and the reading crosstalk phenomenon in a cross array structure can be restrained; meanwhile, the self-gating resistance variable memory unit is suitable for a plane stack cross array structure and a vertical cross array structure, and high-density three-dimensional memory can be realized.

Description

technical field [0001] The invention relates to a self-selecting non-volatile resistive memory unit suitable for a vertical cross array structure and a preparation method thereof, belonging to the technical field of microelectronics. Background technique [0002] The resistive variable memory is a metal / oxide / metal (MIM) capacitor structure, through the action of electrical signals, the device is reversible between the high resistance state (High Resistance State, HRS) and the low resistance state (Low Resistance State, LRS) Conversion, so as to realize the data storage function. Due to its excellent characteristics in terms of cell area, three-dimensional integration, low power consumption, high erasing and writing speed, and multi-value storage, it has attracted great attention at home and abroad. [0003] The array architecture of RRAM can be divided into passive cross array and active array. In the passive cross array, each memory cell is determined by the upper and lo...

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Problems solved by technology

[0006] For the multi-layer stacked structure, the integration of the gate tube and the resistive variable unit can be easily realized through the planar process; but for the vertical cross array structure, the integration of the gate tube is very difficult, because in the vertical array, each column The upper electrode of the resistive switching unit is formed by a trench filling process. Due to the lack of a patterning process for a single device, it is very difficult to integrate a gate tube on each resistive switching unit. Reports of three-dimensional structures are almost all based on single R structures, such as figure 2 As shown, in the absence of a gating tube, the integration scale and read and write operations of this structure will be greatly limited

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