Method for forming semiconductor device

A semiconductor and device technology, applied in the field of semiconductor device formation, can solve the problems that the electrical properties of semiconductor devices need to be improved, achieve the effect of improving short channel effect, reducing the probability of diffusion to the channel region, and improving corrosion resistance

Active Publication Date: 2015-06-10
SEMICON MFG INT (SHANGHAI) CORP
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Problems solved by technology

[0005] However, in the formation process of the actual semiconductor device, it is found that despite the LDD process, the short channel effect in the semiconductor device still exists, and the electrical performance of the semiconductor device still needs to be improved

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  • Method for forming semiconductor device
  • Method for forming semiconductor device
  • Method for forming semiconductor device

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Embodiment Construction

[0035] It can be seen from the background art that there is a short channel effect in semiconductor devices formed in the prior art.

[0036]In order to solve the above problems, the formation method of the semiconductor device is studied. The formation method of the semiconductor device includes the following steps, please refer to figure 1 : step S1, providing a semiconductor substrate, the semiconductor substrate has an isolation structure; step S2, doping the semiconductor substrate between the isolation structures to form a doped well region; step S3; in the semiconductor A gate structure is formed on the surface of the substrate, and the gate structure includes a gate dielectric layer and a gate electrode layer; step S4, forming an offset sidewall layer covering the gate structure and the semiconductor substrate, and the offset sidewall layer The material is silicon nitride; step S5, etch back the offset sidewall layer, remove the offset sidewall layer on the top of the ...

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Abstract

A method for forming a semiconductor device comprises the following steps: providing a semiconductor substrate, wherein gate structures are formed on the surface of the semiconductor substrate; forming offset spacers at the two sides of the gate structures; performing co-doping (including first doping and second doping) on the offset spacers, wherein the first doping is used for capturing defects in the offset spacers, and the second doping improves the content of doped ions in the regions, near the surface of the semiconductor substrate, of the offset spacers; forming lightly doped regions in the semiconductor substrate at the two sides of the gate structures by using the offset spacers as masks; forming main spacers on the side walls of the offset spacers; and forming heavily doped regions in the semiconductor substrate at the two sides of the gate structures by using the main spacers as masks. According to a semiconductor device formed by the method of the invention, the content of boron ions in the semiconductor substrate below the offset spacers is reduced, the probability that boron ions diffuse into a channel region is reduced, the short channel effect of the semiconductor device is improved, and the electrical performance of the semiconductor device is optimized.

Description

technical field [0001] The invention relates to the technology in the field of semiconductor manufacturing, in particular to a method for forming a semiconductor device. Background technique [0002] The main semiconductor device of integrated circuits, especially VLSIs, is metal-oxide-semiconductor field effect transistors (MOS transistors). With the continuous development of integrated circuit manufacturing technology, the technology nodes of semiconductor devices continue to decrease, and the geometric dimensions of semiconductor devices follow Moore's law. [0003] With the rapid development of semiconductor manufacturing technology, the feature size (CD) of semiconductor devices has entered the sub-micron stage. In order to obtain faster computing speed, larger data storage capacity and more functions, semiconductor integrated circuits are constantly developing towards higher component density and high integration. The gate length of metal oxide semiconductor devices,...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8238H01L21/336
CPCH01L21/8238H01L21/823864H01L27/092
Inventor 何有丰
Owner SEMICON MFG INT (SHANGHAI) CORP
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