Thin film transistor manufacturing method

Abstract

The invention discloses a thin film transistor manufacturing method, which comprises the following steps: (1) a chemical vapor deposition method is firstly used for depositing a layer of amorphous silicon on the substrate of the thin film transistor; (2) excimer laser annealer (ELA) technology is used for crystallizing the amorphous silicon to form poly-silicon, and during the crystallizing process, a large number of ridges caused by laser annealing crystallizing are generated on the surface of the poly-silicon; (3) a coating mode is used for manufacturing a flattening layer on the poly-silicon with the ridges to enable the flattening layer to fully cover the ridges of the poly-silicon; and (4) etching is carried out on the flattening layer, when the ridges are etched, the flattening layer and the ridges are etched altogether, and a remaining flattening layer and a remaining small number of ridges are left on the poly-silicon. By adopting the thin film transistor manufacturing method of the invention, the ridge height of the poly-silicon after ELA crystallizing can be greatly reduced, uniformity of AMOLED (Active Matrix Organic Light Emitting Diode) backplane can be improved, and display effects are better.

Description

technical field [0001] The present invention relates to a method for manufacturing a thin film transistor (TFT, Thin Film Transistor) in an active matrix organic light emitting display (AMOLED, Active Matrix Organic Light Emitting Diode), in particular to a method that can effectively reduce excimer laser annealing polysilicon protrusions. A method of fabricating a highly advanced thin film transistor. Background technique [0002] At present, the LTPS (Low Temperature Poly-silicon, low-temperature polysilicon) backplane preparation technology mainly adopts the mainstream crystallization technology of ELA (Excimer Laser Annealer, excimer laser annealing). Under the irradiation of high-energy laser, a-Si (amorphous Silicon) is recrystallized to generate Poly (polysilicon), but this layer of Poly film has obvious protrusions at the grain boundaries of polysilicon, which affects the thickness and step coverage of the subsequent gate oxide layer, mainly affecting the electrical...

AI Technical Summary

Problems solved by technology

[0002] At present, the LTPS (Low Temperature Poly-silicon, low-temperature polysilicon) backplane preparation technology mainly adopts the mainstream crystallization technology of ELA (Excimer Laser Annealer, excimer laser annealing). Under the irradiation of high-energy laser, a-Si (amorphous Silicon) recrystallized to generate Poly (polysilicon), but this layer of Poly film has obvious protrusions at the grain boundary of polysilicon, which affects the thickness and step coverage of the subsequent gate oxide layer, mainly affecting the electrical properties of TFT

Take a-Si thickness of 500 ? as an example to illustrate the impact of this bump: 500 ? , if the protrusion appears in the channel region, the thickness of the gate oxide layer is only 700~800 ? Voltage and source-drain voltage, the TFT with a thinner gate oxide layer (at 700°) is turned on before the TFT with a thicker gate oxide layer (1200°), which reduces the uniformity of Vth (threshold voltage) of the entire backplane , deteriorating the display effect

Images