Distribution of electron beam lithography alignment marks in chip

Abstract

The invention provides distribution of electron beam lithography alignment marks in a chip. The chip comprises a first area and a second area, wherein the second area encloses the first area, the first area comprises the center of the chip, and the electron beam lithography alignment marks are distributed on the second area. A plurality of alignment marks are arranged on the second area and a mark line is arranged between two neighbored alignment marks. The provided distribution can make the manufacture of alignment mark mask be more convenient, the marks can be found more easily during the electron beam overlay process, the distribution can be applied to substrates in any size and shape, multiple groups of alignment marks can be arranged so as to satisfy the multiple alignment exposure of electron beam overlay, and the utilization rate of chips can be increased by the provided distribution.

Description

technical field [0001] The invention relates to the technical field of nano-processing, in particular to a layout of an electron beam lithography alignment mark on a chip. Background technique [0002] Electron beam lithography (or electron beam lithography) is an important top-down nanofabrication manufacturing technology. Its traditional application is to manufacture masks required for optical lithography. With the vigorous development of nanotechnology in recent years, electron beam lithography direct writing technology has become an important means of fabricating and realizing nanoscale structures. [0003] The electron beam lithography process is a serial process, so it is very inefficient. For example, to fully expose an 8-inch wafer and obtain a high-resolution and high-density structure, under the premise of ensuring the quality of the structure, it will take many days even if the fastest electron beam exposure equipment is used (while optical lithography is general...

AI Technical Summary

Problems solved by technology

[0006] First, the wafer mark 102 is very large and is located in the center area of ​​the chip 103, which will occupy a larger area of ​​the chip area and reduce the utilization rate of the chip

[0007] Second, the field of view of the electron microscope of the electron beam lithography equipment is very small, generally tens of microns square, and it takes a long time to find an overlay alignment mark in a chip of a few millimeters square with such a small field of view. Time

[0008] Third, if figure 1 As shown in the layout of the existing electron beam lithography alignment mark on the chip, if a step-and-repeat projection lithography machine is used, two masks need to be made: a wafer marking mask and a chip marking mask. The mask needs to be replaced every moment, which increases the alignment error

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