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Silicon carbide MOSFET device and preparation method thereof

By adopting a stepped gate oxide layer structure in silicon carbide MOSFET devices, the problem of electric field concentration in the gate oxide layer of the device under high voltage is solved, the device's voltage withstand capability and reliability are improved, and the on-resistance is reduced, achieving efficient Power device design.

Inactive Publication Date: 2015-10-07
ZHUZHOU CSR TIMES ELECTRIC CO LTD
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  • Application Information

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Problems solved by technology

But it will increase the on-resistance of the device. On the one hand, it increases the on-resistance of the device. On the other hand, it needs to use high-energy and high-dose aluminum ion implantation, which increases the difficulty of the process and is not conducive to reducing the working loss.

Method used

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Embodiment Construction

[0041] The present invention is further illustrated below by way of examples.

[0042] The results for SiC MOSFET devices in this application are symmetric, figure 1 In ~4, only the region of its left half is shown, and the right half is a mirror image of the left half.

[0043] figure 1 It is a schematic diagram of the traditional SiC MOSFET device structure, including:

[0044] SiC N-type substrate 1 is a highly doped N-type silicon carbide substrate;

[0045] N-type buffer layer 2, which is located on the upper surface of SiC N-type substrate 1, has a thickness of 1-2 μm, N + The doping concentration is 1×10 18 cm -3 magnitude;

[0046] N-type epitaxial layer 3, which is located on the upper surface of buffer layer 2, has a thickness of 10-13 μm, N + The doping concentration is 1×10 15 cm -3 ~9×10 15 cm -3 ;

[0047] JFET region 5, which is located above the middle part of N-type epitaxial layer 3, between adjacent P wells 4, and has a width of 2-6 μm;

[0048]...

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Abstract

The invention relates to a silicon carbide MOSFET device, employing a stepped gate oxide layer structure, wherein a first gate oxide layer is located above a channel and part of an N+ source region and has a thickness of 40-60 nm, and a second gate oxide layer is located above a JFET region, and has a thickness of 100-200 nm. Preferentially, the width of the JFET region of the silicon carbide MOSFET device is 2-6 mu m. The silicon carbide MOSFET devic effectively reduces the electric field intensity of the gate oxide layer, meanwhile does not influence a device threshold voltage and grid control characteristics; and then the silicon carbide MOSFET device can fully expand a design margin, and further reduce device conduction resistance through employing a wider JFET region structure.

Description

technical field [0001] The invention relates to a silicon carbide MOSFET device, in particular to the change of the gate oxide layer thickness above the JFET region of the silicon carbide MOSFET device, and a preparation method of the device. Background technique [0002] Compared with the first-generation semiconductor represented by silicon and the second-generation semiconductor represented by gallium arsenide, the silicon carbide material represented by the third-generation semiconductor has a larger band gap and critical breakdown electric field, making it suitable for manufacturing High voltage and high power semiconductor devices. As a research hotspot in the field of power electronics and new materials in the world, SiC has always been highly valued by the academic community, and has entered the commercialization stage driven by the breakthroughs of companies such as Cree, Rohm, and Infineon. [0003] For a high-performance and high-reliability power device, it need...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/423H01L21/04
CPCH10D64/516H10D62/8325H10D30/60H10D30/66H10D30/0291H10D64/01366H10D12/031H10D62/124H10D62/834H10D84/141H10P14/6308H10P14/6322H10P14/69215
Owner ZHUZHOU CSR TIMES ELECTRIC CO LTD
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