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LED epitaxial layer growing method and LED epitaxial wafer and LED chip obtained by same

An LED epitaxial wafer and LED chip technology, applied in electrical components, circuits, semiconductor devices, etc., can solve problems such as luminous efficiency attenuation, and achieve the effects of improving luminous efficiency attenuation, reducing blocking effect, and improving brightness

Active Publication Date: 2015-11-25
XIANGNENG HUALEI OPTOELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The invention provides a LED epitaxial layer growth method and the resulting LED epitaxial wafer and chip to solve the technical problem of luminous efficiency attenuation under large current injection in the prior art

Method used

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  • LED epitaxial layer growing method and LED epitaxial wafer and LED chip obtained by same
  • LED epitaxial layer growing method and LED epitaxial wafer and LED chip obtained by same
  • LED epitaxial layer growing method and LED epitaxial wafer and LED chip obtained by same

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preparation example Construction

[0041] The specific preparation method is described as follows: Aixtron Cruis I MOCVD (metal organic chemical vapor deposition method) is used to grow the LED epitaxial wafer with the above structure. Using high-purity H 2 and / or N 2 As a carrier gas, high-purity NH 3 As the N source, the metal-organic source trimethylgallium (TMGa), triethylgallium is used as the gallium (TEGa) source, trimethylindium (TMIn) is used as the indium source, and the N-type dopant is silane (SiH 4 ), the P-type dopant is magnesocene (CP2Mg), the substrate is (0001) plane sapphire, and the reaction pressure is 100mbar-800mbar.

[0042] 1. Raise the temperature to 1100°C, and maintain the pressure of the reaction chamber at 150mbar to treat the sapphire substrate at high temperature for 5 minutes in a hydrogen atmosphere;

[0043] 2. Cool down to 550°C, maintain the pressure of the reaction chamber at 600mbar, and grow a low-temperature buffer layer GaN with a thickness of 30nm on the sapphire su...

Embodiment 1

[0054] 1. Raise the temperature to 1100°C, and maintain the pressure of the reaction chamber at 150mbar to treat the sapphire substrate at high temperature for 5 minutes in a hydrogen atmosphere;

[0055] 2. Cool down to 550°C, maintain the pressure of the reaction chamber at 600mbar, and grow a low-temperature buffer layer GaN with a thickness of 30nm on the sapphire substrate;

[0056] 3. Raise the temperature to 1050°C, maintain the pressure in the reaction chamber at 600mbar, and continue to grow 3μm undoped GaN;

[0057] 4. Then continue to grow N-type GaN doped with Si, the Si doping concentration is 1E+19atom / cm3, and the total thickness is controlled at 4μm;

[0058] 5. Periodically grow the active layer MQW, maintain the pressure of the reaction chamber at 300mbar, (1) cool down to 750°C, and grow In with a thickness of 3.2nm 0.25 Ga 0.75 N well layer; (2) increase the temperature to 850°C, and grow a GaN barrier layer with a thickness of 12nm; repeat the growth ste...

Embodiment 2

[0064] The difference with embodiment 1 is:

[0065] 6. Periodically grow a superlattice layer as an electron blocking layer, control the temperature at 1000°C, control the pressure in the reaction chamber at 600mbar, and grow 2nm P-type In 0.2 Ga 0.8 N layer and 2nm P-type Al 0.02 Ga 0.98 N layer, Mg doping concentration 1E+20; change the TMIn and TMAl doping concentration of the MOCVD (metal organic chemical vapor deposition) reaction chamber, and continue to grow 2nm P-type In 0.18 Ga 0.82 N layer and 2nm P-type Al 0.04 Ga 0.96 N layer, Mg doping concentration is 1E+20; (other steps not described in detail are the same as in Example 1); according to the above method, 10 cycles of In x Ga (1-x) N / Al y Ga (1-y) N superlattice electron blocking layer, where x is 0.2, 0.18, 0.16, 0.14, 0.12, 0.1, 0.08, 0.06, 0.04, 0.02, y is 0.02, 0.04, 0.06, 0.08, 0.1, 0.12, 0.14, 0.16 , 0.18, 0.2, the total thickness of the electron blocking layer is 40nm.

[0066] Other steps rema...

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Abstract

The invention provides an LED epitaxial layer growing method, and an LED epitaxial wafer and a chip obtained by the same. The LED epitaxial layer growing method comprises the following steps: S1, growing a super-lattice layer on a multiple-quantum well layer; and S2, growing a P-type GaN layer on the super-lattice layer. The super-lattice layer includes multiple superposed unit structures, and each unit structure is composed of a P-type InxGa(1-x)N layer and a P-type AlyGa(1-y)N layer superposed on the P-type InxGa(1-x)N layer, wherein x=0-0.2, and y=0-0.4. Through adjustment, the unit structures meet the following conditions: x=0.2-a*(n - 1) and y=b*n, wherein n is the serial number of the corresponding unit structure in the super-lattice layer, a is the x difference between adjacent unit structures, and b is the y difference between adjacent unit structures. Therefore, the energy band of the super-lattice layer changes in a stepped way. By adopting the method, the attenuation problem of luminous efficiency under high current injection can be improved, and the forward voltage of the LED chip can be reduced while the brightness is increased.

Description

technical field [0001] The invention relates to the field of growing LED epitaxial wafers, in particular to a method for growing LED epitaxial layers and the obtained LED epitaxial wafers and chips. Background technique [0002] LED (light-emitting diode) is a semiconductor device that can directly convert electrical energy into light energy. Compared with traditional light sources, LEDs have the advantages of long life, small size, fast response, and high luminous efficiency. At present, LED devices have been widely used in the fields of electrical indicator lights, color screen backlights and daily lighting. In order to solve the problem of LED luminous efficiency attenuation (efficiency droop) under high current injection, people insert AlGaN layer, AlGaN / GaN superlattice or AlGaN / InGaN superlattice and other electrons between the quantum well layer and the P-type GaN layer. The blocking layer (electron blocking layer, EBL) blocks electrons by increasing the band gap, s...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L33/00H01L33/04H01L33/32
CPCH01L33/005H01L33/0075H01L33/04H01L33/32H01L33/325
Inventor 农明涛苗振林卢国军徐平
Owner XIANGNENG HUALEI OPTOELECTRONICS