Low-temperature sintering nano-silver paste and preparation process thereof

Abstract

The invention discloses a process for preparing low-temperature sintering nano-silver paste. The process comprises the following steps: 1) preparing blank reverse microemulsion and making a pseudoternary phase diagram; 2) preparing the reverse microemulsion containing nano-silver particles; 3) performing centrifugal separation: performing centrifugal separation on the reverse microemulsion containing the nano-silver particles 2-4 times, separating oil phase organic matter and aqueous phase solution, and obtaining the nano-silver particles adsorbed by mixed surfactants; 4) causing the nano-silver particles adsorbed by the mixed surfactants obtained in the step 3) to be mixed with organic carriers, adjusting the viscosity, and preparing the low-temperature sintering nano-silver paste. The process has the advantages that the nano-silver particles are wrapped with the surfactants from nucleation growth to the formation of final slurry, the hard aggregation of the nano-silver particles is greatly reduced, the nano-silver particles prepared through the process are controllable in size, and the preparation process is simplified.

Description

technical field [0001] The invention relates to a material preparation technology, in particular to a low-temperature sintered nano-silver paste and a preparation process. Background technique [0002] Compared with the first and second generation semiconductor materials, the third-generation semiconductor represented by silicon carbide has a wider band gap, high breakdown voltage, high thermal conductivity, high electron saturation and more High radiation resistance. These characteristics enable the third-generation semiconductor to withstand higher power density, but this also poses higher challenges to its packaging. As the material closest to the chip, the interconnection material between the chip and the substrate is extremely important for the performance of the chip. Impact. [0003] Traditional interconnection materials between chips and substrates—solder alloys and conductive adhesives are difficult to meet the demand due to fatal defects. Alloy solder has the di...

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Problems solved by technology

These characteristics enable the third-generation semiconductor to withstand higher power density, but this also poses higher challenges to its packaging. As the material closest to the chip, the interconnection material between the chip and the substrate is extremely important for the performance of the chip. Impact

[0003] Traditional chip-to-substrate interconnection materials—solder alloys and conductive adhesives are difficult to meet demand due to fatal defects

Alloy solder has the disadvantage of low reliability at high temperature. At the same time, the alloy solder has a large thermal stress under the working state of the device, which may easily cause the chip to fail due to the mismatch of thermal expansion coefficient; the thermal conductivity of the conductive adhesive is low, usually at 10-25W / m·K, and the glass transition temperature of the conductive adhesive is low. As the use time increases, the resin matrix of the conductive adhesive will gradually experience fatigue failure, and the thermal resistance will increase, which is extremely unfavorable for the heat dissipation and physical properties of the chip.

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