Method for realizing silicon-silicon bonding by using diffusion and mutual dissolution of metal material
A technology of metal materials and metal silicides, applied in the field of semiconductor manufacturing, to achieve the effects of increasing bonding strength, loose bonding conditions, and excellent bonding airtightness
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Embodiment 1
[0031] Embodiment 1, concrete process is as follows:
[0032] (1) Get a first silicon wafer 1, which is a single-polish N-type (100) substrate, carry out inorganic cleaning, and rinse the surface of the wafer with a buffered hydrofluoric acid solution;
[0033] (2) Get a second silicon wafer 3, which is a single-polish N-type (100) substrate, carry out inorganic cleaning, and rinse the surface of the wafer with a buffered hydrofluoric acid solution;
[0034] (3) Adopt Denton magnetron sputtering system, prepare film layer 2 on the first silicon chip 1, the material of this film layer 2 is W, and thickness is
[0035] (4) Place the side of the first silicon wafer 1 prepared with the thin film layer 2 and the second silicon wafer 3 in the SUSS bonding machine, vacuumize and raise the temperature to 500 ° C, and then use the disc pressure method to bond the A pressure of 2000N was applied to the sheet, and it was maintained at 500°C and a pressure of 2000N for 30 minutes. Aft...
Embodiment 2
[0036] Embodiment 2, concrete process is as follows:
[0037] (1) Get a first silicon chip 1, which is a double-polishing N-type (100) substrate, carry out inorganic cleaning, and rinse the surface of the chip with a buffered hydrofluoric acid solution;
[0038] (2) Get a second silicon chip 3, which is a double-throwing N-type (100) substrate chip, carry out inorganic cleaning, and rinse the chip surface with a buffered hydrofluoric acid solution;
[0039] (3) adopt Denton magnetron sputtering system, prepare film layer 2 on the first silicon chip 1, the material of this film layer 2 is Ti, and thickness is And the thin film layer 2 is patterned according to the requirements of the device packaging cavity.
[0040] (4) A cavity structure is prepared on the first silicon wafer 1 by using an ICP etching process, and the etching depth is determined according to device packaging requirements.
[0041] (5) The first silicon chip 1 with the cavity structure is prepared with the ...
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