Method for Increasing Control Gate Height of Split Gate Flash Memory

Abstract

The present invention proposes a method for increasing the height of the control gate of the sub-gate flash memory. Firstly, the high-voltage gate dielectric layer with an uneven thickness on the surface of the polysilicon is removed, and then a dielectric layer with a relatively uniform thickness is formed on the surface of the polysilicon, so that the polysilicon is subsequently etched. When , the dielectric layer near the top of the polysilicon sidewall can not be severely etched, so that the polysilicon sidewall can be protected, so that the formed word line has a higher recess height, avoiding the penetration of subsequent ion implantation, and improving device performance .

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for increasing the height of a control gate of a sub-gate flash memory. Background technique [0002] Random access memory (such as DRAM and SRAM) has the problem of data loss after power failure during use. [0003] In order to overcome this problem, various flash memories have been designed and developed. The flash memory based on the floating gate concept has become a more general flash memory due to its smaller cell size and good working performance. [0004] Flash memory includes two basic structures: stack gate and split gate. Among them, the gate stack flash memory includes: a tunnel oxide layer formed on the semiconductor substrate in sequence, a floating silicon nitride layer for storing electrons, a control oxide layer, and a control gate polysilicon layer for controlling electron storage and release. , that is, the SONOS structure. The split-gate...

AI Technical Summary

Problems solved by technology

Because the high-voltage gate oxide layer 40 is formed in the device region (Cell), and the thickness of the high-voltage gate oxide layer 40 at the top of the polysilicon 11 is thinner than that of the sidewall of the polysilicon 11, and the gas or gas with a relatively low etching selectivity for the two is used. The acid solution etches the polysilicon 11. Therefore, the high voltage gate oxide layer 40 at the top of the sidewall of the polysilicon 11 will be severely etched, and the sidewall of the polysilicon 11 cannot be protected. Thus, the polysilicon 11 is formed with a concave height H2 and a corner The height H3 is low, and it is easy to be penetrated later, causing PTC problems. In addition, the high-voltage gate oxide layer 40 at the bottom of the sidewall cannot be etched clean, and it is easy to form residual

Images