A method for efficiently electroplating and filling silicon-based TSVs

Abstract

The invention discloses a method for efficiently electroplating and filling silicon-based TSV. The method specifically comprises the steps of etching and preparing the TSV on a wafer; preparing an insulating layer on the wafer for etching the TSV; preparing a seed layer on the wafer containing the insulating layer; enabling dry films to the adhered to the two surfaces of the wafer, and performing single-surface photoetching and developing; removing the seed layer from the TSV side wall port position; enabling the dry film to be adhered to the patterned surface and developing the other surface; removing the seed layer from the other port position again; then performing photoetching and developing again; next, performing bisynchronous electroplate copper filling to enable TSV-Cu and TSV-pad to be integrally molded without a separating interface; and removing the dry films, the photoresist and the seed layers. According to the method, the TSV through hole electroplating filling process is converted into two blind-hole-like electroplating filling processes, so that the TSV structure can be firmly combined; the process is more flexible and convenient; the high-aspect-ratio TSV through hole electroplating filling difficulty is greatly lowered; and meanwhile, the electroplating efficiency is effectively improved, and the low-cost and efficient TSV preparation can be realized.

Description

technical field [0001] The present invention relates to the field of microelectronic packaging, in particular, to a high-efficiency filling method based on through-holes, that is, a method for filling TSVs by bidirectional synchronous electroplating by dividing the middle of the through-holes into two blind holes. This method is suitable for low-cost silicon-based TSVs. Efficient fill preparation. Background technique [0002] With the rapid development of the semiconductor industry, the requirements for miniaturization and multi-functional integration of microsystems are increasingly urgent, with the advantages of high-speed interconnection, high-density integration, miniaturization, and homogeneous and heterogeneous functional integration. Packaging (3D-TSV) has gradually become one of the most popular researches in semiconductor packaging technology. Although 3D-TSV packaging technology has many advantages, there are still some unfavorable factors restricting the develop...

AI Technical Summary

Problems solved by technology

These processes are still immature, which restricts the application and development of 3D-TSV packaging technology

[0003] The thermal mechanical reliability and electrical performance reliability of 3D-TSV packaging technology is a huge challenge for this process technology to achieve mass production

Residual stress and thermal stress between the interface between Cu-TSV and TSV-pad naturally exist, and TSV filling is blind hole filling, and subsequent processes such as wafer thinning after electroplating will lead to the accumulation of residual stress and warping. Curve, which directly affects the thermomechanical stability and electrical properties of TSV

At the same time, traditional TSV through-hole filling is difficult to achieve hole-free filling because of the difficulty in controlling the plating rate at the end of the deep hole.

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