Full back electrode contact crystalline silicon solar cell structure and preparation method thereof
A full-back electrode contact and solar cell technology, applied in the field of solar cells, can solve the problems of high material cost, recombination loss, and resistance loss, etc., and achieve the effects of reducing the amount of silver electrodes used, reducing recombination loss, and improving conversion efficiency
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Embodiment 1
[0056] (1) The N-type monocrystalline silicon wafer is anisotropically etched in a KOH solution at about 80°C to obtain a pyramid structure on the surface.
[0057] (2) on the front side of the silicon chip, with PClO 3 As impurities, low-pressure thermal diffusion is performed at about 700-850°C to form a uniform N+ layer of 80Ω / □.
[0058] (3) The phosphorosilicate glass and the back junction on the front side are removed by wet etching.
[0059] (4) Deposit 20nm of silicon oxide on the front side of the silicon wafer, and then deposit 50nm of silicon nitride.
[0060] (5) An intrinsic amorphous silicon layer of about 10 nm is deposited on the back surface of the silicon wafer.
[0061] (6) On the intrinsic amorphous silicon layer on the back of the silicon wafer, a P and N-type amorphous silicon layer of about 10 nm is produced by chemical vapor deposition cooperative masking and photolithography, and the P and N-type amorphous silicon layers on the back Alternately arra...
Embodiment 2
[0069] (1) The N-type monocrystalline silicon wafer is anisotropically etched in a KOH solution at about 80°C to obtain a pyramid structure on the surface.
[0070] (2) by pH 3 As impurities, a uniform N+ layer of 100Ω / □ is formed on the front side of the silicon wafer by ion implantation.
[0071] (3) Perform annealing treatment on the silicon wafer after ion implantation.
[0072] (4) Deposit 20nm of silicon oxide on the front side of the silicon wafer, and then deposit 70nm of silicon nitride.
[0073] (5) A tunneling silicon oxide film of about 1.5 nm is deposited on the back side of the silicon wafer.
[0074] (6) On the tunneling silicon oxide film on the back of the silicon wafer, P and N-type amorphous silicon layers of 12 nm are alternately arranged by chemical vapor deposition cooperative masking and photolithography. The width of a single P-type amorphous silicon strip region on the back is 1.2mm, and the width of a single N-type amorphous silicon strip region on...
Embodiment 3
[0082] (1) The N-type monocrystalline silicon wafer is anisotropically etched in a KOH solution at about 80°C to obtain a pyramid structure on the surface.
[0083] (2) by pH 3As impurities, a uniform N+ layer of 100Ω / □ is formed on the front side of the silicon wafer by ion implantation.
[0084] (3) Perform annealing treatment on the silicon wafer after ion implantation.
[0085] (4) Chemically cleaning the doped silicon wafer.
[0086] (5) Deposit 80nm silicon nitride on the front side of the silicon wafer.
[0087] (6) An intrinsic amorphous silicon layer of about 13 nm is deposited on the back side of the silicon wafer.
[0088] (7) On the intrinsic amorphous silicon layer on the back of the silicon wafer, a P and N-type amorphous silicon layer of about 10 nm is produced by chemical vapor deposition cooperative masking and photolithography. Alternately arranged on the intrinsic amorphous silicon layer. The width of a single P-type amorphous silicon strip region on th...
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Abstract
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