Negatron compression rate-ultra-steep sub-threshold slope field effect transistor and preparation method thereof

Abstract

The present invention discloses a negatron compression rate-ultra-steep sub-threshold slope field effect transistor and a preparation method thereof. According to the technical scheme of the invention, in the sub-threshold region of a device, a first conventional gate dielectric layer and a second conventional gate dielectric layer form a conventional gate dielectric capacitor. A negatron compression-rate gate dielectric layer forms an NEC capacitor. In this way, the capacitance value of the conventional gate dielectric capacitor is larger than the absolute value of the NEC capacitor, so that the above two series capacitors are negative in value. The gate control coefficient is less than 1 and the gate leakage current is inhibited. As a result, the gate voltage has an exceptional control capability over the surface of a channel, so that the device is ultra-steep in sub-threshold slope. Meanwhile, considering the variation at the electronic scale, the NEC capacitor of the device enables the macroscopic properties of the device to be free of the hysteresis and the material fatigue resistance any more. Therefore, on the basis that the power consumption of the device is reduced, the NCFET problem of the traditional ferroelectric material is solved. For the industry development of low-power-consumption integrated circuits in the future, the negatron compression rate-ultra-steep sub-threshold slope field effect transistor and the preparation method thereof have a wide application prospect.

Description

technical field [0001] The invention relates to a logic device of a field effect transistor, in particular to a negative electron compressibility-ultrasteep subthreshold slope field effect transistor and a preparation method thereof. Background technique [0002] Since the 20th century, the integrated circuit industry has been driven by the two wheels of economy and technology with the continuous rapid development of Moore's Law. Today, the traditional metal-oxide semiconductor field effect transistor MOSFET feature size has been reduced to the nanometer scale, but the ensuing challenges The problems brought about by the shrinking device size are also becoming more and more serious. The continuous proportional reduction of devices makes the short channel effect more and more serious. The hot electron effect, the leakage-induced barrier lowering effect and the breakdown of the drain PN junction will cause the increase of the off-state current. At the same time, the traditiona...

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Problems solved by technology

However, due to the limitation of the lattice structure of ferroelectric materials, ferroelectric NCF

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